基于vhdl的fpga串口通信

clkrstrxdtxd:OUTstd_logic;--clkrstrxdtxd:OUTstd_logic;--串行数据发送端基于vhdl的fpga串口通信-本模块的功能是验证实现和pc机进行差不多的串口通信的功能。需要在-PC机上安装一个串口调试工具来验证程序的功能。-程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控-制器，10个bit是1位起始位，8个数据位，1个终止-位。串口的波特律由程序中定义的div_par参数决定，更换该参数能够实-现相应的波特率。程序当前设定的div_par的值是0x104，对应的波特率是-9600。用一个8倍波特率的时钟将发送或同意每一位bit的周期时刻-划分为8个时隙以使通信同步.-程序的工作过程是：串口处于全双工工作状态，按动 key2,CPLD向PC发送阜elcome"-字符串（串口调试工具设成按ASCII码同意方式）；PC可随时向CPLD发送0-F的十六进制--数据，CPLD同意后显示在7段数码管上。libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYUARTISPORT(:INstd_logic;:INstd_logic;:INstd_logic;--串行数据接收端enOUTstd_logic_vector(7downtoen:OUTstd_logic_vector(7DOWNTO:INstd_logic:OUTstd_logic_vector(7DOWNTO:INstd_logic--按键输入0);--数码管数据key_input);ENDUART;ARCHITECTUREarchOFUARTIS--//////////////////innerreg////////////////////SIGNALdiv_reg:std_logic_vector(15DOWNTO0);--分频计数器，分频值由波特率决定。分频后得到频率 8倍波特率的时钟SIGNALdiv8_tras_reg:std_logic_vector(2DOWNTO0);--该寄存器的计数值对应发送时当前位于的时隙数SIGNALdiv8_rec_reg:std_logic_vector(2DOWNTO0);--寄存器的计数值对应接收时当前位于的时隙数SIGNALstate_trasOSIGNALstate_trasO0);--发送状态寄存器SIGNALstate_recO0);--同意状态寄存器SIGNALclkbaud_tras率的发送使能信号SIGNALclkbaud_rec率的同意使能信号std_logic_vector(3DOWNTstd_logic_vector(3DOWNTstd_logic;--以波特率为频std_logic;--以波特率为频SIGNALclkbaud8x:std_logic;--以8倍波特率为频率的时钟，它的作用是将发送或同意一个bit的时钟周期分为8个时隙 _SIGNALrecstart: s也10gg--开始发送标志SIGNALrecstart_tmp: std_1ogic;--开始同意标志SIGNALtrasstart:SIGNALrxd_reg1SIGNALrxd_reg2SIGNALtrasstart:SIGNALrxd_reg1SIGNALrxd_reg2因为接收数据为异步信号，故用两级缓存SIGNALtxd_regSIGNALrxd_bufTO0);--同意数据缓存SIGNALtxd_bufTO0);--发送数据缓存SIGNALsend_state:O0);--每次按键给PC发送"We1come"字符串,SIGNALcnt_delayNTO0);--延时去抖计数器SIGNALstart_delaycnt标志SIGNALkey_entry1下曛？SIGNALkey_entry2下标志std_logic;:std_logic;--接收寄存器1:std_logic;--接收寄存器2，:std_logic;--发送寄存器:std_logic_vector(7DOWN:std_logic_vector(7DOWNstd_logic_vector(2DOWNT这是发送状态寄存器:std_logic_vector(19DOWstd_logic;--开始延时计数:std_logic;--确定有键按:std_logic;--确定有键按--//////////////////////////////////////////////CONSTANTdiv_par std_logic_vector(15DOWNTO0):="0000000100000100";--分频参数，其值由对应的波特率运算而得，按此参数分频的时钟频率是波倍特率的8倍，此处值对应9600的波特率，即分频出的时钟频率是9600*8SIGNALtxd_xhdl3 :std_logic;BEGINen〈=”01010101”；--7段数码管使能信号赋值txd<=txd_xhdl3;txd_xhdl3<=txd_reg;PROCESS(clk,rst)BEGINIF(NOTrst='1')THENcnt_delay<=”00000000000000000000”;start_delaycnt<='0';ELSIF(clk'EVENTANDclk='1')THENIF(start_delaycnt='1')THENIF(cnt_delay/=”11000011010100000000”)THENcnt_delay+”00000000000000000001”;cnt_delay<=ELSEcnt_delay<=”00000000000000000000”;start_delaycnt<='0';ENDIF;ELSEIF((NOTkey_input='1')AND(cnt_delay=”00000000000000000000”))THENstart_delaycnt<='1';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,rst)BEGINIF(NOTrst='1')THENkey_entry1<='0';ELSIF(clk'EVENTANDclk='1')THENIF(key_entry2='1')THENkey_entry1<='0';ELSEIF(cnt_delay="11000011010100000000")THENIF(NOTkey_input='1')THENkey_entry1<='1';ENDIF;ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,rst)BEGINIF(NOTrst='1')THENdiv_reg<="0000000000000000";ELSIF(clk'EVENTANDclk='1')THENIF(div_reg=div_par-"0000000000000001")THENdiv_reg<="0000000000000000";ELSEdiv_reg<=div_reg+"0000000000000001";ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,rst)--分频得至I」8倍波特率的时钟BEGINIF(NOTrst='1')THENclkbaud8x<='0';ELSIF(clk'EVENTANDclk='1')THENIF(div_reg=div_par-"0000000000000001")THENclkbaud8x<=NOTclkbaud8x;ENDIF;ENDIF;ENDPROCESS;PROCESS(clkbaud8x,rst)BEGINIF(NOTrst='1')THENdiv8_rec_reg<="000";ELSEIF(clkbaud8x'EVENTANDclkbaud8x='1')THENIF(recstart='1')THEN--接收开始标志div8_rec_reg<=div8_rec_reg+"001";--接收开始后，时隙数在8倍波特率的时钟下加1循环ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clkbaud8x,rst)BEGINIF(NOTrst='1')THENdiv8_tras_reg<="000";ELSEIF(clkbaud8x'EVENTANDclkbaud8x='1')THENIF(trasstart='1')THENdiv8_tras_reg<=div8_tras_reg+"001";--发送开始后，时隙数在8倍波特率的时钟下加1循环ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(div8_rec_reg)BEGINIF(div8_rec_reg="111")THENclkbaud_rec<='1';---在第7个时隙，接收鼓苄藕庞行 B荽蛉？ELSEclkbaud_rec<='0';ENDIF;ENDPROCESS;PROCESS(div8_tras_reg)BEGINIF(div8_tras_reg="111")THENclkbaud_tras<='1';--在第7个时隙，发送使能信号有效，将数据发出ELSEclkbaud_tras<='0';ENDIF;ENDPROCESS;PROCESS(clkbaud8x,rst)BEGINIF(NOTrst='1')THENtxd_reg<='1';trasstart<='0';txd_buf<="00000000";state_tras<="0000";send_state<="000";key_entry2<='0';ELSEIF(clkbaud8x'EVENTANDclkbaud8x='1')THENIF(NOTkey_entry2='1')THENIF(key_entry1='1')THENkey_entry2<='1';txd_buf<="01110111";--"w"ENDIF;ELSECASEstate_trasISWHEN"0000"=>--发送起始位IF((NOTtrasstart='1')AND(send_state<"111"))"111"))THENtrasstart<='1';ELSEIF(send_statetrasstart<='1';ELSEIF(send_state<"111")THENIF(clkbaud_tras='1')THENtxd_reg<='0';state_tras<=state_tras+"0001ENDIF;ELSEkey_entry2<='0';state_tras<="0000";ENDIF;ENDIF;WHEN"0001"=>--发送第1位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTODOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"0010"=>--发送第2位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_trasDOWNTO1);ENDIF;WHEN"0011"=>--发送第3位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"0100"=>--发送第4位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"0101"=>--发送第5位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"0110"=>--发送第6位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"0111"=>--发送第7位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"1000"=>--发送第8位IF(clkbaud_tras='1')THENtxd_reg<=txd_buf(0);txd_buf(6DOWNTO0)<=txd_buf(7DOWNTO1);state_tras<=state_tras+"0001";ENDIF;WHEN"1001"=>--发送停止位IF(clkbaud_tras='1')THENtxd_reg<='1';txd_buf<="01010101";state_tras<=state_tras+"0001";ENDIF;WHEN"1111"=>IF(clkbaud_tras='1')THENstate_tras<=state_tras+"0001";send_state<=send_state+"001";trasstart<='0';CASEsend_stateISWHEN"000"=>txd_buf<="01100101";WHEN"001"=>txd_buf<="01101100";"l"WHEN"010"=>txd_buf<="01100011";--"c"WHEN"011"=>txd_buf<="01101111";"o"WHEN"100"=>txd_buf<="01101101";--"m"WHEN"101"=>txd_buf<="01100101";"e"WHENOTHERS=>txd_buf<="00000000";ENDCASE;ENDIF;WHENOTHERS=>IF(clkbaud_tras='1')THENstate_tras<=

state_tras+"0001";trasstart<='1';ENDIF;ENDCASE;ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clkbaud8x,rst)--同意PC机的数据BEGINIF(NOTrst='1')THENrxd_reg1<='0';rxd_reg2<='0';rxd_buf<="00000000";state_rec<="0000";recstart<='0';recstart_tmp<='0';ELSEIF(clkbaud8x'EVENTANDclkbaud8x='1')THENrxd_reg1<=rxd;rxd_reg2<=rxd_reg1;IF(state_rec="0000")THENIF(recstart_tmp='1')THENrecstart<='1';recstart_tmp<='0';state_rec<=state_rec+"0001";ELSEIF((NOTrxd_reg1ANDrxd_reg2)='1')THEN--检测到起始位的下降沿，进入同意状态recstart_tmp<='1';ENDIF;ENDIF;ELSEIF(state_rec>="0001"ANDstate_rec<="1000")THENIF(clkbaud_rec='1')THENrxd_buf(7)<=rxd_reg2;rxd_buf(6DOWNTO0)<=rxd_buf(7DOWNTO1);state_rec<=state_rec+"0001";ENDIF;ELSEIF(state_rec="1001")THENIF(clkbaud_rec='1')THENstate_rec<="0000";recstart<='0';ENDIF;ENDIF;