vhdl课程设计-简单处理器的设计与仿真

-PAGE33-前言 11、设计任务 22、设计说明 32.1处理器原理图及其组成 32.2数据传输及加减法的实现 32.3处理器所支持的指令及功能说明、指令的编码规则 42.4指令执行的时序控制 43.处理器指令实现的功能及其具体描述 63.1mvRx,Ry 63.2mviRx,#D 73.3addRx,Ry和subRx,Ry 84单元模块设计说明、VHDL代码及其仿真 104.1寄存器RX 104.2寄存器A 114.3加/减法器addsub 124.4寄存器G 134.5指令寄存器IR 144.6计数器upcount 154.7复用器multi 164.8控制单元control 184.9控制指令输入转换模块 264.1016*16点阵显示控制模块 275处理器各个模块的连接及处理器功能仿真 295.1处理器各个模块的连接 295.2处理器功能仿真 295.2.1立即数赋给寄存器R0 295.2.2立即数赋给寄存器R1 295.2.3寄存器R0的值赋给寄存器R2 295.2.4寄存器R1的值赋给寄存器R3 295.2.5立即数赋给寄存器R4 295.2.6寄存器R0加上R4赋给R0 305.2.7寄存器R1加上R4赋给R1 305.2.6寄存器R0加上R4赋给R0 305.2.7立即数赋给寄存器R5 305.2.8寄存器R4减去R5赋给R4 305.2.9寄存器R4减去R0赋给R4 306处理器实现的功能与操作说明 316.1处理器实现的功能 316.2处理器相关的操作说明 317课程设计总结 328附录……………………...……34前言VHDL的英文全名是Very-High-SpeedIntegratedCircuitHardwareDescriptionLanguage，诞生于1982年。1987年底，VHDL被IEEE和美国国防部确认为标准硬件描述语言。VHDL主要用于描述数字系统的结构，行为，功能和接口。除了含有许多具有硬件特征的语句外，VHDL的语言形式和描述风格与句法是十分类似于一般的计算机高级语言。VHDL的程序结构特点是将一项工程设计，或称设计实体（可以是一个元件，一个电路模块或一个系统）分成外部（或称可是部分,及端口)和内部（或称不可视部分），既涉及实体的内部功能和算法完成部分。在对一个设计实体定义了外部界面后，一旦其内部开发完成后，其他的设计就可以直接调用这个实体。这种将设计实体分成内外部分的概念是VHDL系统设计的基本点。与其他硬件描述语言相比，VHDL具有以下特点：（1）功能强大、设计灵活VHDL具有功能强大的语言结构，可以用简洁明确的源代码来描述复杂的逻辑控制。它具有多层次的设计描述功能，层层细化，最后可直接生成电路级描述。VHDL支持同步电路、异步电路和随机电路的设计，这是其他硬件描述语言所不能比拟的。VHDL还支持各种设计方法，既支持自底向上的设计，又支持自顶向下的设计；既支持模块化设计，又支持层次化设计。（2）支持广泛、易于修改由于VHDL已经成为IEEE标准所规范的硬件描述语言，目前大多数EDA工具几乎都支持VHDL，这为VHDL的进一步推广和广泛应用奠定了基础。在硬件电路设计过程中，主要的设计文件是用VHDL编写的源代码，因为VHDL易读和结构化，所以易于修改设计。（3）强大的系统硬件描述能力VHDL具有多层次的设计描述功能，既可以描述系统级电路，又可以描述门级电路。而描述既可以采用行为描述、寄存器传输描述或结构描述，也可以采用三者混合的混合级描述。另外，VHDL支持惯性延迟和传输延迟，还可以准确地建立硬件电路模型。VHDL支持预定义的和自定义的数据类型，给硬件描述带来较大的自由度，使设计人员能够方便地创建高层次的系统模型。（4）独立于器件的设计、与工艺无关设计人员用VHDL进行设计时，不需要首先考虑选择完成设计的器件，就可以集中精力进行设计的优化。当设计描述完成后，可以用多种不同的器件结构来实现其功能。（5）很强的移植能力VHDL是一种标准化的硬件描述语言，同一个设计描述可以被不同的工具所支持，使得设计描述的移植成为可能。（6）易于共享和复用VHDL采用基于库（Library）的设计方法，可以建立各种可再次利用的模块。这些模块可以预先设计或使用以前设计中的存档模块，将这些模块存放到库中，就可以在以后的设计中进行复用，可以使设计成果在设计人员之间进行交流和共享，减少硬件电路设计。1、设计任务用VHDL设计一个简单的处理器，并完成相关的仿真测试。2、设计说明2.1处理器原理图及其组成图1是一个处理器的原理图，它包含了一定数量的寄存器、一个复用器、一个加法/减法器（Addsub）,一个计数器和一个控制单元。图1简单处理器的电路图2.2数据传输及加减法的实现数据传输实现过程：16位数据从DIN输入到系统中，可以通过复用器分配给R0~R7和A，复用器也允许数据从一个寄存器传通过Bus送到另外一个寄存器。加法和减法的实现过程：复用器先将一个数据通过总线放到寄存器A中，然后将另一个数据放到总线上，加法/减法器对这两个数据进行运算，运算结果存入寄存器G中，G中的数据又可根据要求通过复用器转存到其他寄存器中。2.3处理器所支持的指令及功能说明、指令的编码规则表1是该处理所支持的指令表1操作功能说明mvRx,RyRx←[Ry]将Ry寄存器的值复制到Rx寄存器mviRx,#DRx←Data将Data值存入Rx寄存器addRx,RyRx←[Rx]+[Ry]先将Rx和Ry寄存器的值相加，再把相加的值存入Rx寄存器subRx,RyRx←[Rx]-[Ry]先将Rx和Ry寄存器的值相减，再把相减的值存入Rx寄存器所有指令都按9位编码（取自DIN的高9位）存储在指令寄存器IR中，编码规则为IIIXXXYYY，III表示指令，XXX表示Rx寄存器，YYY表示Ry寄存器。立即数#D是在mvi指令存储到IR中之后，通过16位DIN输入的。如表2所示表22.4指令执行的时序控制有一些指令，如加法指令和减法指令，需要在总线上多次传输数据，因此需要多个时钟周期才能完成。控制单元使用了一个两位计数器来区分这些指令执行的每一个阶段。当Run信号置位时，处理器开始执行DIN输入的指令。当指令执行结束后，Done信号置位，表3列出四个指令在执行过程中每一个时间段置位的控制信号。图2列出了处理器的状态转换图表3：时间指令T0T1T2T3(mv):I0(mvi):I1(add):I2(sub):I3IRinIRinIRinIRinRYout,RXin,DoneDINout,RXin,DoneRXout,AinRXout,AinRYout,Gin,AddsubRYout,Gin,AddsubGout,RXin,DoneGout,RXin,Done““00”IRin“10”Add/sub“01”mv“11”Add/sub“01”Add/sub“01”mvi“10”Add/sub图2，处理器状态转换图3.处理器指令实现的功能及其具体描述3.1mvRx,Ry实现的功能：将寄存器Rx的值赋给寄存器Ry（以mvR0,R5为例）（1）计数器为“00”时,指令寄存器的置位控制信号输入端IRin=1有效，将DIN输入的数据的高9位锁存。置位的控制信号如图3加粗黑线所示。图3（2）计数器为“01”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制信号让R5的值输出到总线上，然后控制单元控制寄存器R0将总线上的值锁存，完成整个寄存器对寄存器的赋值过程。置位的控制信号和数据流如图4加粗黑线所示。图43.2mviRx,#D实现的功能：将的立即数#D赋给寄存器Rx（以mvR0,#D为例）（1）计数器为“00”时,指令寄存器的置位控制信号输入端IRin=1有效，将DIN输入的数据的高9位锁存。置位的控制信号如图5加粗黑线所示。图5（2）计数器为“01”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制信号让DIN的值输出到总线上，然后控制单元控制寄存器R0将总线上的值锁存，完成整个立即数对寄存器的赋值过程。置位的控制信号和数据流如图6加粗黑线所示。图63.3addRx,Ry和subRx,Ry实现的功能：将寄存器Ry的值加上/减去寄存器Rx的值并赋给寄存器Rx（以add/subR0,R1为例）。（1）计数器为“00”时,指令寄存器的置位控制信号输入端IRin=1有效，将DIN输入的数据的高9位锁存。置位的控制信号如图7加粗黑线所示。图7（2）计数器为“01”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制信号让R0的值输出到总线上，然后控制单元控制寄存器A将总线上的值锁存。置位的控制信号和数据流如图8加粗黑线所示。图8（3）计数器为“10”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制信号让R1的值输出到总线上，然后控制单元控制加法/减法器addsub将寄存器A的值和总线上的值相加/相减并输出，接着寄存器G将加法/减法器addsub的计算结果锁存。置位的控制信号和数据流如图9加粗黑线所示。图9（4）计数器为“11”时,首先控制单元向复用器发出选通控制信号，复用器根据该控制信号让寄存器G的值输出到总线上，寄存器R0将总线上的值进行锁存，完成整个寄存器与对寄存器见加减法的运算过程。置位的控制信号和数据流如图10加粗黑线所示。图104单元模块设计说明、VHDL代码及其仿真4.1寄存器RX寄存器R0~R7用于数据的存储。当时钟输入clock的上升沿到来且RXin=1时，将数据输入端datain[15..0]的数据锁存到寄存器中并从数据输出端dataout[15..0]输出；当RXin=0时，输出端保持原来的值不变。图11寄存器RX的VHDL代码：libraryieee;useieee.std_logic_1164.all;entityRXisport(RXin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endRX;architecturebehaveofRXissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,RXin,datain,databuffer)beginif(clock'eventandclock='1')thenif(RXin='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.2寄存器A寄存器A用于数据的存储，当时钟输入clock的上升沿到来且Ain=1时，将数据输入端datain[15..0]的数据锁存到寄存器中并从数据输出端dataout[15..0]输出；当RXin=0时，输出端保持原来的值不变。当处理加减法时，将时间T1时总线送过来的数据暂存，当T2时，将T1时存储在A中的数据与总线传输过来的数据在Addsub中进行加减运算，并将结果并输出到寄存器G中。图12寄存器A的VHDL代码：libraryieee;useieee.std_logic_1164.all;entityAisport(Ain,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endA;architecturebehaveofAissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,Ain,datain,databuffer)beginif(clock'eventandclock='1')thenif(Ain='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.3加/减法器addsub加/减法器addsub用于处理两个输入的数据datain2[15..0]和datain1[15..0]，当控制端Addsub=1时，两个数据输入端datain2[15..0]和datain1[15..0]相加并从数据输出端dataout[15..0]输出；当控制端Addsub=0时，数据输入端datain2[15..0]减去datain1[15..0]，结果从数据输出端dataout[15..0]输出。图13加/减法器addsub的VHDL代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaddsubisport(Addsub:instd_logic;datain1:instd_logic_vector(15downto0);datain2:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endaddsub;architecturebehaveofaddsubissignaldatabuffer:std_logic_vector(15downto0);beginprocess(Addsub,datain1,datain2,databuffer)beginif(Addsub='1')thendatabuffer<=datain2+datain1;elsif(Addsub='0')thendatabuffer<=datain2-datain1;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.4寄存器G寄存器G用于加减运算结果的存储，当时钟输入clock的上升沿到来且Gin=1时，将数据输入端datain[15..0]的数据锁存到寄存器中并从数据输出端dataout[15..0]输出；当RXin=0时，输出端保持原来的值不变。图14寄存器G的VHDL代码：libraryieee;useieee.std_logic_1164.all;entityGisport(Gin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endG;architecturebehaveofGissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,Gin,datain,databuffer)beginif(clock'eventandclock='1')thenif(Gin='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.5指令寄存器IR指令寄存器IR用于对输入的16为指令进行处理，取其高9位。当时钟输入clock的上升沿到来且IRin=1时，取数据输入端datain[15..0]的高9位将其锁存到寄存器中并从数据输出端dataout[8..0]输出；当RXin=0时，输出端保持原来的值不变。图15指令寄存器IR的VHDL代码libraryieee;useieee.std_logic_1164.all;entityIRisport(IRin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(8downto0));endIR;architecturebehaveofIRissignaldatabuffer:std_logic_vector(8downto0);beginprocess(clock,IRin,datain,databuffer)beginif(clock'eventandclock='1')thenif(IRin='1')thendatabuffer<=datain(15downto7);elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.6计数器upcount计数器upcount用于产生控制单元的输入脉冲，对控制单元的工作时序进行控制。当clear=0时（清零端clear无效），时钟输入clock每来一个上升沿，输出Q[1..0]加1，所以输出为00——>01——>10——>11——>00不断循环；当clear=1时（清零端clear有效），对输出Q[1..0]异步清零，与时钟无关。图16计数器upcount的VHDL代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityupcountisport(clear,clock:instd_logic;Q:outstd_logic_vector(1downto0));endupcount;architectureBehaviorofupcountissignalcount:std_logic_vector(1downto0);beginprocess(Clock)beginif(clock'eventandclock='1')thenifclear='1'thenclear='1'cleariseffectivecount<="00";elsecount<=count+1;endif;endif;endprocess;Q<=count;endBehavior;4.7复用器multi复用器根据控制单元的控制信号将指定的输入数据输出到总线上。来自控制单元的控制信号为R0out~R7out、Gout、DINout，输入数据位来自寄存器R0~R7、寄存器A、数据输入端DIN，当控制信号的某一位为1时，将其对应的输入数据输出到总线上。图17复用器multi的VHDL代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitymultiisport(R0in:instd_logic_vector(15downto0);R1in:instd_logic_vector(15downto0);R2in:instd_logic_vector(15downto0);R3in:instd_logic_vector(15downto0);R4in:instd_logic_vector(15downto0);R5in:instd_logic_vector(15downto0);R6in:instd_logic_vector(15downto0);R7in:instd_logic_vector(15downto0);DIN:instd_logic_vector(15downto0);Gin:instd_logic_vector(15downto0);R0out:instd_logic;R1out:instd_logic;R2out:instd_logic;R3out:instd_logic;R4out:instd_logic;R5out:instd_logic;R6out:instd_logic;R7out:instd_logic;Gout:instd_logic;DINout:instd_logic;buswire:bufferstd_logic_vector(15downto0));endmulti;architecturebehaveofmultiissignalselect_signal:std_logic_vector(9downto0);signaldatabuffer:std_logic_vector(15downto0);beginselect_signal<=R7out&R6out&R5out&R4out&R3out&R2out&R1out&R0out&Gout&DINout;process(databuffer,R0in,R1in,R2in,R3in,R4in,R5in,R6in,R7in,DIN,Gin,R7out,R6out,R5out,R4out,R3out,R2out,R1out,R0out,Gout,DINout)begincaseselect_signaliswhen"0000000001"=>databuffer<=DIN;when"0000000010"=>databuffer<=Gin;when"0000000100"=>databuffer<=R0in;when"0000001000"=>databuffer<=R1in;when"0000010000"=>databuffer<=R2in;when"0000100000"=>databuffer<=R3in;when"0001000000"=>databuffer<=R4in;when"0010000000"=>databuffer<=R5in;when"0100000000"=>databuffer<=R6in;when"1000000000"=>databuffer<=R7in;whenothers=>null;endcase;buswire<=databuffer;endprocess;endbehave;4.8控制单元control控制单元根据计数器发出的脉冲和DIN输入的操作指令对整个系统的其他模块进行控制，完成指定的操作。图18控制单元control的VHDL代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitycontrolisport(Run:instd_logic;Reset:instd_logic;DIN_IR_9:instd_logic_vector(8downto0);count:instd_logic_vector(1downto0);IRin:outstd_logic;Gout:outstd_logic;DINout:outstd_logic;R0in,R1in,R2in,R3in,R4in,R5in,R6in,R7in:outstd_logic;R0out,R1out,R2out,R3out,R4out,R5out,R6out,R7out:outstd_logic;Gin:outstd_logic;Ain:outstd_logic;Addsub:outstd_logic;Done:outstd_logic;clear:outstd_logic);endcontrol;architecturebehaveofcontrolis--typestateis(state0,state1,state2,state3);--signalcurrent_state,next_state:state;signalIR_buffer:std_logic_vector(8downto0);--signaltemp0:std_logic_vector(2downto0);beginprocess(Run,reset,count)beginIR_buffer<=DIN_IR_9;if(Run='1'andreset='0')thencasecountiswhen"00"=>IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';IRin<='1';state1when"01"=>tttttttttttttttttttttttttttttttttttttttttif(IR_buffer(8downto6)="000")thenmvRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(2downto0)iswhen"000"=>R0out<='1';--test1_signal<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"001"=>R1out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"010"=>R2out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"011"=>R3out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"100"=>R4out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"101"=>R5out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"110"=>R6out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"111"=>R7out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;whenothers=>null;endcase;Done<='1';clear<='1';tttttttttttttttttttttttttttttttttttttttttelsif(IR_buffer(8downto6)="001")thenmviRx,#Dstate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';DINout<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;Done<='1';clear<='1';========================================pppppppppppppppppppppppppppppppppppppppelsif(IR_buffer(8downto6)="010")thenaddRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(5downto3)iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Ain<='1';pppppppppppppppppppppppppppppppppppppppcccccccccccccccccccccccccccccccccccccccccelsif(IR_buffer(8downto6)="011")thensubRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(5downto3)iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Ain<='1';endif;cccccccccccccccccccccccccccccccccccccccccstate1state2state2state2when"10"=>if(IR_buffer(8downto6)="000")thenmvwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="001")thenmviwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="010")thenaddRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';case(IR_buffer(2downto0))iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Addsub<='1';Gin<='1';elsif(IR_buffer(8downto6)="011")thensubRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';case(IR_buffer(2downto0))iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Addsub<='0';Gin<='1';endif;state2state2state2state3state3state3state3when"11"=>if(IR_buffer(8downto6)="000")thenmvwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="001")thenmviwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="010"orIR_buffer(8downto6)="011")thenaddRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';Gout<='1';case(IR_buffer(5downto3))iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;Done<='1';endif;state3state3state3state3whenothers=>null;endcase;endif;endprocess;endbehave;4.9控制指令输入转换模块由于试验箱上只有12个拨动开关，而16位控制指令只有高9位有效，低7位只有在赋立即数时有用到。为了方便操作，将波动开关K1~K9接输入控制指令DIN的高9位，波动开关K11和K12分别接Run和Reset的输入。控制指令DIN的低7位全部用0填充。图19控制指令输入转换模块的VHDL代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityin9_out16isport(operate_in_9:instd_logic_vector(8downto0);operate_out_16:outstd_logic_vector(15downto0));endin9_out16;architecturebehaveofin9_out16issignaltemp:std_logic_vector(15downto0);begintemp<=operate_in_9&'0'&'0'&'0'&'0'&'0'&'0'&'0';operate_out_16<=temp;endbehave;4.1016*16点阵显示控制模块将寄存器R0~R7的值显示在16*16点阵上，具体显示规则为：列对应某个寄存器的值，从左到右为R0~R7，其中每两列有效的显示列间都间隔1列全部灭灯以方便观察；行对应特定寄存器的不同位，从上到下为寄存器的地位到高位RX（0）~RX(15)。图2016*16点阵显示控制模块的VHDL代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityled_matrixisport(clk:instd_logic;R0_in:instd_logic_vector(15downto0);R1_in:instd_logic_vector(15downto0);R2_in:instd_logic_vector(15downto0);R3_in:instd_logic_vector(15downto0);R4_in:instd_logic_vector(15downto0);R5_in:instd_logic_vector(15downto0);R6_in:instd_logic_vector(15downto0);R7_in:instd_logic_vector(15downto0);keyc:outstd_logic_vector(15downto0);--点阵列控制keyr:outstd_logic_vector(15downto0)--点阵行显示);endled_matrix;architecturebehaveofled_matrixissignalcdount:std_logic_vector(3downto0);signaldount:std_logic_vector(8downto0);signalS:std_logic_vector(3downto0);beginprocess(clk)--显示时序控制beginifclk'eventandclk='1'thenifcdount<15thencdount<=cdount+1;elsecdount<="0000";endif;endif;endprocess;process(cdount)begincasecdountiswhen"0000"=>keyc<="0000000000000001";when"0001"=>keyc<="0000000000000010";when"0010"=>keyc<="0000000000000100";when"0011"=>keyc<="0000000000001000";when"0100"=>keyc<="0000000000010000";when"0101"=>keyc<="0000000000100000";when"0110"=>keyc<="0000000001000000";when"0111"=>keyc<="0000000010000000";when"1000"=>keyc<="0000000100000000";when"1001"=>keyc<="0000001000000000";when"1010"=>keyc<="0000010000000000";when"1011"=>keyc<="0000100000000000";when"1100"=>keyc<="0001000000000000";when"1101"=>keyc<="0010000000000000";when"1110"=>keyc<="0100000000000000";when"1111"=>keyc<="1000000000000000";whenothers=>keyc<="0000000000000000";endcase;casecdountiswhen"0000"=>keyr<=R0_in;when"0001"=>keyr<="1111111111111111";when"0010"=>keyr<=R1_in;when"0011"=>keyr<="1111111111111111";when"0100"=>keyr<=R2_in;when"0101"=>keyr<="1111111111111111";when"0110"=>keyr<=R3_in;when"0111"=>keyr<="1111111111111111";when"