8051系列微控制器-毕业论文外文文献翻译毕业论文

PAGEPAGE17英文资料及中文翻译OverviewThe8051familyofmicrocontrollersisbasedonanarchitecturewhichishighlyoptimizedforembeddedcontrolsystems.ItisusedinawidevarietyofapplicationsfrommilitaryequipmenttoautomobilestothekeyboardonyourPC.SecondonlytotheMotorola68HC11ineightbitprocessorssales,the8051familyofmicrocontrollersisavailableinawidearrayofvariationsfrommanufacturerssuchasIntel,Philips,andSiemens.Thesemanufacturershaveaddednumerousfeaturesandperipheralstothe8051suchasI2Cinterfaces,analogtodigitalconverters,watchdogtimers,andpulsewidthmodulatedoutputs.Variationsofthe8051withclockspeedsupto40MHzandvoltagerequirementsdownto1.5voltsareavailable.Thiswiderangeofpartsbasedononecoremakesthe8051familyanexcellentchoiceasthebasearchitectureforacompany'sentirelineofproductssinceitcanperformmanyfunctionsanddeveloperswillonlyhavetolearnthisoneplatform.Thebasicarchitectureconsistsofthefollowingfeatures:1aneightbitALU232descreteI/Opins(4groupsof8)whichcanbeindividuallyaccessed3two16bittimer/counters4fullduplexUART56interruptsourceswith2prioritylevels6128bytesofonboardRAM7separate64KbyteaddressspacesforDATAandCODEmemoryOne8051processorcycleconsistsoftwelveoscillatorperiods.Eachofthetwelveoscillatorperiodsisusedforaspecialfunctionbythe8051coresuchasopcodefetchesandsamplesoftheinterruptdaisychainforpendinginterrupts.Thetimerequiredforany8051instructioncanbecomputedbydividingtheclockfrequencyby12,invertingthatresultandmultiplyingitbythenumberofprocessorcyclesrequiredbytheinstructioninquestion.Therefore,ifyouhaveasystemwhichisusingan11.059MHzclock,youcancomputethenumberofinstructionspersecondbydividingthisvalueby12.Thisgivesaninstructionfrequencyof921583instructionspersecond.Invertingthiswillprovidetheamountoftimetakenbyeachinstructioncycle(1.085microseconds).MemoryOrganizationThe8051architectureprovidestheuserwiththreephysicallydistinctmemoryspaceswhichcanbeseeninFigureA-1.Eachmemoryspaceconsistsofcontiguousaddressesfrom0tothemaximumsize,inbytes,ofthememoryspace.Addressoverlapsareresolvedbyutilizinginstructionswhichreferspecificallytoagivenaddressspace.Thethreememoryspacesfunctionasdescribedbelow.TheCODESpaceThefirstmemoryspaceistheCODEsegmentinwhichtheexecutableprogramresides.Thissegmentcanbeupto64K(sinceitisaddressedby16addresslines).TheprocessortreatsthissegmentasreadonlyandwillgeneratesignalsappropriatetoaccessamemorydevicesuchasanEPROM.However,thisdoesnotmeanthattheCODEsegmentmustbeimplementedusinganEPROM.ManyembeddedsystemsthesedaysareusingEEPROMwhichallowsthememorytobeoverwritteneitherbythe8051itselforbyanexternaldevice.ThismakesupgradestotheproducteasytodosincenewsoftwarecanbedownloadedintotheEEPROMratherthanhavingtodisassembleitandinstallanewEPROM.Additionally,batterybackedSRAMcanbeusedinplaceofanEPROM.ThismethodoffersthesamecapabilitytouploadnewsoftwaretotheunitasdoesanEEPROM,anddoesnothaveanysortofread/writecyclelimitationssuchasanEEPROMhas.However,whenthebatterysupplyingtheRAMeventuallydies,sodoesthesoftwareinit.UsinganSRAMinplaceofanEPROMindevelopmentsystemsallowsforrapiddownloadingofnewcodeintothetargetsystem.Whenthiscanbedone,ithelpsavoidthecycleofprogramming/testing/erasingwithEPROM,andcanalsohelpavoidhasslesoveranincircuitemulatorwhichisusuallyararecommodity.Inadditiontoexecutablecode,itiscommonpracticewiththe8051tostorefixedlookuptablesintheCODEsegment.Tofacilitatethis,the8051providesinstructionswhichallowrapidaccesstotablesviathedatapointer(DPTR)ortheprogramcounterwithanoffsetintothetableoptionallyprovidedbytheaccumulator.Thismeansthatoftentimes,atable'sbaseaddresscanbeloadedinDPTRandtheelementofthetabletoaccesscanbeheldintheaccumulator.Theadditionisperformedbythe8051duringtheexecutionoftheinstructionwhichcansavemanycyclesdependingonthesituation.Anexampleofthisisshownlaterinthischapterin.TheDATASpaceThesecondmemoryspaceisthe128bytesofinternalRAMonthe8051,orthefirst128bytesofinternalRAMonthe8052.ThissegmentistypicallyreferredtoastheDATAsegment.TheRAMlocationsinthissegmentareaccessedinoneortwocyclesdependingontheinstruction.ThisaccesstimeismuchquickerthanaccesstotheXDATAsegmentbecausememoryisaddresseddirectlyratherthanviaamemorypointersuchasDPTRwhichmustfirstbeinitialized.Therefore,frequentlyusedvariablesandtemporaryscratchvariablesareusuallyassignedtotheDATAsegment.Suchallocationmustbedonewithcare,however,duetothelimitedamountofmemoryinthissegment.VariablesstoredintheDATAsegmentcanalsobeaccessedindirectlyviaR0orR1.Theregisterbeingusedasthememorypointermustcontaintheaddressofthebytetoberetrievedoraltered.Theseinstructionscantakeoneortwoprocessorcyclesdependingonthesource/destinationdatabyte.TheDATAsegmentcontainstwosmallersegmentsofinterest.Thefirstsubsegmentconsistsofthefoursetsofregisterbankswhichcomposethefirst32bytesofRAM.The8051canuseanyofthesefourgroupsofeightbytesasitsdefaultregisterbank.TheselectionofregisterbanksischangeableatanytimeviatheRS1andtheRS0bitsintheProcessorStatusWord(PSW).Thesetwobitscombineintoanumberfrom0to3(withRS1beingthemostsignificantbit)whichindicatestheregisterbanktobeused.Registerbankswitchingallowsnotonlyforquickparameterpassing,butalsoopensthedoorforsimplifyingtaskswitchingonthe8051.Thesecondsub-segmentintheDATAspaceisabitaddressablesegmentinwhicheachbitcanbeindividuallyaccessed.ThissegmentisreferredtoastheBDATAsegment.Thebitaddressablesegmentconsistsof16bytes(128bits)abovethefourregisterbanksinmemory.The8051containsseveralsinglebitinstructionswhichareoftenveryusefulincontrolapplicationsandaidinreplacingexternalcombinatoriallogicwithsoftwareinthe8051thusreducingpartscountonthetargetsystem.Itshouldbenotedthatthese16bytescanalsobeaccessedona"byte-wide"basisjustlikeanyotherbyteintheDATAspace.SpecialFunctionRegistersControlregistersfortheinterruptsystemandtheperipheralsonthe8051arecontainedininternalRAMatlocations80hexandabove.Theseregistersarereferredtoasspecialfunction.Registers(orSFRforshort).Manyofthemarebitaddressable.ThebitsinthebitaddressableSFRcaneitherbeaccessedbyname,indexorbitaddress.Thus,youcanrefertotheEAbitoftheInterruptEnableSFRasEA,IE.7,or0AFH.TheSFRcontrolthingssuchasthefunctionofthetimer/counters,theUART,andtheinterruptsourcesaswellastheirpriorities.TheseregistersareaccessedbythesamesetofinstructionsasthebytesandbitsintheDATAsegment.AmemorymapoftheSFRSindicatingtheregisters.TheIDATASpaceCertain8051familymemberssuchasthe8052containanadditional128bytesofinternalRAMwhichresideatRAMlocations80hexandabove.ThissegmentofRAMistypicallyreferredtoastheIDATAsegment.BecausetheIDATAaddressesandtheSFRaddressesoverlap,addressconflictsbetweenIDATARAMandtheSFRsareresolvedbythetypeofmemoryaccessbeingperformed,sincetheIDATAsegmentcanonlybeaccessedviaindirectaddressingmodes.TheXDATASpace.Thefinal8051memoryspaceis64Kinlengthandisaddressedbythesame16addresslinesastheCODEsegment.Thisspaceistypicallyreferredtoastheexternaldatamemoryspace(ortheXDATAsegmentforshort).ThissegmentusuallyconsistsofsomesortofRAM(usuallyanSRAM)andtheI/Odevicesorexternalperipheralstowhichthe8051mustinterfaceviaitsbus.ReadorwriteoperationstothissegmenttakeaminimumoftwoprocessorcyclesandareperformedusingeitherDPTR,R0,orR1.InthecaseofDPTR,itusuallytakestwoprocessorcyclesormoretoloadthedesiredaddressinadditiontothetwocyclesrequiredtoperformthereadorwriteoperation.Similarly,loadingR0orR1willtakeminimumofonecycleinadditiontothetwocyclesimposedbythememoryaccessitself.Therefore,itiseasytoseethatatypicaloperationwiththeXDATAsegmentwill,ingeneral,takeaminimumofthreeprocessorcycles.Becauseofthis,theDATAsegmentisaveryattractiveplacetostoreanyfrequently.Itispossibletofillthissegmententirelywith64KofRAMifthe8051doesnotneedtoperformanyI/OwithdevicesinitsbusorifthedesignerwishestocycletheRAMonandoffwhenI/Odevicesarebeingaccessedviathebus.Methodsforperformingthistechniquewillbediscussedinchapterslaterinthisbook.On-BoardTimer/CountersThestandard8051hastwotimer/counters(other8051familymembershavevaryingamounts),eachofwhichisafull16bits.Eachtimer/countercanbefunctionasafreerunningtimer(inwhichcasetheycountprocessorcycles)orcanbeusedtocountfallingedgesonthesignalappliedtotheirrespectiveI/Opin(eitherT0orT1).Whenusedasacounter,theinputsignalmusthaveafrequencyequaltoorlowerthantheinstructioncyclefrequencydividedby2(ie:theoscillatorfrequency/24)sincetheincomingsignalissampledeveryinstructioncycle,andthecounterisincrementedonlywhena1to0transitionisdetected(whichwillrequiretwosamples).Ifdesired,thetimer/counterscanforceasoftwareinterruptwhentheyoverflow.TheTCON(TimerControl)SFRisusedtostartorstopthetimersaswellasholdtheoverflowflagsofthetimers.TheTCONSFRisdetailedbelowinTableA-7.Thetimer/countersarestartedorstoppedbychangingthetimerrunbits(TR0andTR1)inTCON.ThesoftwarecanfreezetheoperationofeithertimeraswellasrestartthetimerssimplybychangingtheTrxbitintheTCONregister.TheTCONregisteralsocontainstheoverflowflagsforthetimers.Whenthetimersoverflow,theysettheirrespectiveflag(TF0orTF1)inthisregister.Whentheprocessordetectsa0to1transitionintheflag,aninterruptoccursifitisenabled.Itshouldbenotedthatthesoftwarecansetorclearthisflagatanytime.Therefore,aninterruptcanbepreventedaswellasforcedbythesoftware.MicrocomputerinterfaceAmicrocomputerinterfaceconvertsinformationbetweentwoforms.Outsidethemicrocomputertheinformationhandledbyanelectronicsystemexistsasaphysicalsignals,butwithintheprogram,itisrepresentednumerically.Thefunctionofanyinterfacecanbebrokendownintoanumberofoperationswhichmodifythedatainsomeway,sothantheprocessofconversionbetweentheexternalandinternalformsiscarriedoutinanumberorsteps.ThiscanbeillustratedbymeansofanexamplesuchasthanorFig10-1,whichshowsaninterfacebetweenamicrocomputerandatransducerproducingacontinuouslyvariableanalogsignal.transducersoftenproduceverysmalloutrequiringamplyfrication,ortheymaygeneratesignals.inaformthatneedstobeconvertedagainbeforebeinghandledbytherestofthesystem.Forexample,manytransducersthesevariableresistancewhichmustbeconvertedtoavoltagebyaspecialcircuit.Thisprocessofconvertingthetransduceroutputintoavoltage4signalwhichcanbeconnectedtotherestofthesystemiscalledsignalconditioning.IntheexampleofFigure10-1,thesigmaconditioningsectiontranslatestherangelfvoltageorcurrentsignalsfromthetransducertoonewhichcanbeconvertedtodigitalforumbyananalog-to-digitalconverter.TransducerADCSignalconditioningTransducerADCSignalconditioningI/OSectionI/OSectionFig10-1outputInterfaceAnalog-to-digital–digitalconverter(ADC)isusedtoconvertacontinuouslyvariablesignaltoacorrespondingdigitalforumwhichcantakeanyoneofafixednumberofpossiblebinaryvalues.Iftheoutputlfthetransducerdoesnotvarycontinuously,noADCisnecessary.Inthiscasethesignalconditioningsectionmustconverttheincomingsignaltoaformwhichcanbeconnecteddirectlytothenextpartoftheinterface,theinput/outputsectionlfthemicrocomputeritself.TheI/Osectionconvertsdigital“on/off”voltagesignalstoaformwhichcanbepresentedtotheprocessorviatheviathesystembuses.Herethestateofeachinputlinewhetheritis“on”or“off”,isindicatedbyacorresponding“1”or“0”.Inthelineinputswhichhavebeenconvertedtodigitalform,thepatternsofonesandzerosintheinternalrepresentationwillformbinarynumberscorrespondingtothequantitybeingconverted.The“raw”numbersfromtheinterfacearelimitedbythedesignoftheinterfacecircuitryandtheyoftenrequirelinearizationandscalingtoproducevaluessuitableforuseinthemainprogram.Forexample,theinterfacenightberisetoconverttemperaturesintherange–20to–+50dress,buythenumbersproducedbyan8-bitconverterwilllieintherange0to255.Obviouslyitiseasier,theprogrammer‘spointofviewtodealdirectlywithtemperatureratherthantoworkouttheequivalentofanygiventemperatureintermsofthenumbersproducedbytheADC.Everytimetheinterfaceisusedtoreadatransducer,thesameoperationsmustbecarriedouttoconverttheinputnumberintoamoreconvenientform.Addtionarly,theoperationofsomeinterfacesrequirescontrolsignalstobepassedbetweenthemicrocomputerandcomponentsoftheinterface,Forthesereasonsitisnormaltouseasubroutinetolootafterthedetailedoperationoftheinterfaceandcarryoutanyscalingand/orlinearizationwhichmightbeneeded.Outputinterfacestakeasimilarform(Fig.10-2),thebiopicdifferencebeingthatheretheflowofinformationisintheoppositedirection;itispassedfromtheprogramtotheoutsideworld.Inthiscasetheprogrammaycallanoutputsubroutinewhichsupervisestheoperationoftheinterfaceandperformsthescalingnumberswhichmaybeneededforadigital-to-analogconverter(DAC).ThissubroutinepassesinformationintermtoanoutanalogformusingaDAC.Finallythesignalisconditioned(usuallyamplified)toaformsuitableforoperatinganactuator.Fig10-2outputInterfaceThesignalsusedwithinmicrocomputercircuitsarealmostalwaystoosmalltobeconnecteddirectlytothe“outsideworld”andsomekingofinterfacemustbeusedtotranslatethemtoamoreappropriateform.Thedesignofsectionofinterfacecircuitsisoneofthemostimportanttasksfacingtheengineerwishingtoapplymicrocomputers.Wehaveseenthatinmicrocomputersinformationisrepresentedasdiscretepatternsofbits;thisdigitalformismostusefulwhenthemicrocomputeristobeconnectedtoequipmentwhichcanonlybeswitchedonoroff,whereeachbitmightrepresentthestateofaswitchoractuator.Caremustbetakenwhenconnectinglogiccircuitstoensurethattheirlogiclevelsandcurrentratingsarecompatible.Theoutputvoltagesproducedbyalogiccircuitarenormallyspecifiedintermsofworstcasevalueswhensourcingorsinkingthemaximumratedcurrents.ThusVOHistheguaranteedminimum“high”voltagewhensourcingthemaximumrate“high”outputcurrentIOH,whileVOListheguaranteed“low”outputvoltagewhensinkingthemaximumrated“low”outputcurrentIOL.Therearecorrespondingspecificationsforlogicinputswhichspecifytheminimuminputvoltagewhichwillberecognizedasalogic“high”stateVIH,andthemaximuminputvoltagewhichwillberegardedasalogic“low”stateVIL.Forinputinterface,perhapsthemainproblemfacingthedesigneristhatofelectricalnoise.Smallnoisesignalmaycausethesystemtomalfunction,whilelargeramountsofmoistcanpermanentlydamageit.Thedesignermustbeawareofthesedangersfromtheoutset.Therearemanymethodstoprotectinterfacecircuitsandmicrocomputerfromvariouskindsofnoise.Followingissomeexamples:1.Inputandoutputelectricalisolatingbetweenthemicrocomputersystemandexternaldevicesusinganopt-isolatororatransformer.2.Removinghighfrequencynoisepulsesbyalow-peafilterandSchmitt-trigger.3.Protectingagainstexcessiveinputvoltagesusingapairofdiodestopowersupplyreversiblybiasedinnormaldirection.Foroutputinterface,parametersVOH,VOL,IOHandIOLofalogicdeviceareusuallymuchtolowtoallowloadstobeconnecteddirectly,andinpracticeanexternalcircuitmustbeconnectedtoamplifythecurrentandvoltagetodriveaload.AlthoughseveraltypesofsemiconductordevicesarenowavailableforcontrollingDCandACpowersuptomanykilowatts,therearetwobasicwaysinwhichaswitchcanbeconnectedtoaloadtocontrolit:seriesconnectionandshuntconnectionasshowninFigure10-3.Fig10-3SeriesandShuntConnectionWithseriesconnection,theswitchallowscurrenttoflowthroughtheloadwhenclosed,whilewithshuntconnectionclosingtheswitchallowscurrenttobypasstheload.Bothconnectionsareusefulinlow-powercircuits,butonlytheseriesconnectioncanbeusedinhigh-powercircuitsbecauseofthepowerwastedintheseriesresistorR.THEINTRODUCTIONOFAT89C52FeaturesoftheAT89C52•CompatiblewithMCS-51™Products•8KBytesofIn-SystemReprogrammableFlashMemory•Endurance:1,000Write/EraseCycles•FullyStaticOperation:0Hzto24MHz•Three-levelProgramMemoryLock•256x8-BitInternalRAM•32ProgrammableI/OLines•Three16-bitTimer/Counters•EightInterruptSources•ProgrammableSerialChannel•LowPowerIdleandPowerDownModesDescriptionTheAT89C52isalow-power,high-performanceCMOS8-bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51and80C52instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89C52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitectureafullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89C52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAMtimer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthardwarereset.PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighby.Theinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.TABLE1--PortPinfunctionPortpinAlternateFunctionsP1.0T2(externalcountinputtoTimer/Counter2),clock-outP1.1T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)Port2Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.概述 8051系列微控制器是基于高度完善的嵌入式控制系统的体系结构。从军事设备到汽车，再到PC机的键盘，它都有很广泛的应用。另外，对于摩托罗拉公司生产的M68HC11（8位处理器）可以应用于不同厂商生产的8051系列微控制器，如：Intel、Philips及Siemens等。这些厂商都对8051增加了许多功能部件和外围设备，如：12C总线接口、模/数转换器、监视跟踪定时器和脉冲宽度调制输出。8051的允许范围：时钟频率上至40MHz，电压下至1.5V都是有效的。一个公司的生产线要完成许多功能，开发人员就不得不学习这个平台，为此以8051系列作为基本体系结构是最好的选择，以它为核心得到了广泛的应用。基本体系结构由下列功能部件组成：1.8位ALU；2.32个I/O引脚（4组，每组8个），可分别存取；3.2个16位定时/计数器；4.全双工通用异步收发器；5.6个中断源，2个中断优先级；6.128字节随机存储器；7.64字节地址空间，存放数据和代码。一个8051的处理器周期是由12个振荡周期组成。12个振荡周期中每一个都能完成一种特殊功能，8051的核心如：操作码的取出、典型的菊花链待定中断。任何8051指令所需的定时都是由时钟脉冲频率除以12，再将所得结果乘以处理机所需的循环数计算得到。因此，如果你有一个系统时钟11.059MHz，你可以用这个值除以12计算出每秒所需指令数。这里我们给出一个指令频率921583/秒。将它转化成实际时间，每个指令周期（1.085微妙）。存储器组织8051体系结构为用户提供了3个物理直接存储空间。每个存储空间占用连续地址空间，按字节从0到最大尺寸。地址重叠是通过利用引用特定地址空间指令来解决的。这三个存储空间功能如下所述：代码空间第一个存储空间是代码段，其中用来存放可执行程序。这个段最大可达64K（因为它有16根地址线）。处理机将它视为只读，能产生相应的信号对一存储器件进行存取，如可擦可编程只读存储器EPROM。然而，这不意味着代码段必须作为EPROM的工具。目前，许多嵌入式系统都利用EPROM，通过8051或一个外部设备允许对它存储或改写。这可能轻而易举的提高产品，因为新的软件可以下载到EPROM，而不必将它分解后再安装成一个新的EPROM。另外，电池后面的静态存储器SRAM也可用来代替EPROM。这种方法和加载软件到电可擦可编程只读存储器EEPROM是一样的，但是EEPROM没有任何读/写周期限制。然而，当电池电源RAM没电了，也可如此将软件加载到里面。在开发系统中若用SRAM代替EPROM，则允许在目标系统中快速下载新代码。如果可以那样做，它将帮助我们避免对EPROM的循环执行/测试/擦写，同时也能帮助我们避免对通常很少使用的线路仿真器产生争论。除可执行程序代码之外，8051通常在代码段存放安装查找表。为了简化，8051提供了允许快速存取查找表指令的途径——数据指针（DPTR）或带偏移量的程序计数器通过累加器随意的指向查找表。通常这意味着，一个查找表的基地址能用DPTR来定位，而表中的元素可以通过累加器存储。用8051执行加法，在指令执行期间可以根据情况存放许多循环数。数据空间8051辅助存储空间是128字节的内部RAM，而8052的高128字节是辅助存储空间。这个段被认为是典型的数据段。RAM定位在这个段，依靠指令循环存取一次或二次。这样存取时间比存取在XDATA段要快很多，因为存储器直接给出地址，胜于由存储指针如DPTR必须先初始化。因此，通常将已用变量和临时定义变量都放在数据段。然而，这样的分配会占用段中少量的存储单元。数据段中的可变存储器还可以由R0或R1间接存储。使用寄存器作存储指针就必须包含已检索或已改变字节的地址。这些指令可以依靠源/目的数据字节使一个或二个处理机循环。数据段又包含两个重要的小段。第一个子段由四个寄存器组组成，它占用了RAM的低32字节。8051用这四组（每组8字节）作为缺省寄存器组。寄存器组选定区域在任何时候都通过处理机状态字（PSW）中的RS1和RS0这两位来改变。这两位组合表示数0~3（RS1作最高有效位），用来指明哪个寄存器组在被使用。在8051中，寄存器组开关不但允许快速参数传递，而且能打开单任务开关。在数据空间的第二个子段是一个可寻址位段，每一位都能单独存取。这个段称为BDATA段。可寻址的位段由内存中四个寄存器组16字节（128位）组成。8051包含许多位指令，它通常用于控制某一位的应用及在8051中用软件替换外部组合逻辑给予帮助，这样在目标系统中以减少部分依赖。人们注意到这个16字节还可以按“一位”宽在数据空间像其他字节一样进行存取。特殊功能寄存器8051内部RAM的80H以上的单元为控制寄存器，包含中断系统和外部设备。这些寄存器称为特殊功能寄存器（简称SFR）。它们大部分是可按位寻址的。在可按位寻址的SFR中的位可以是被访问的名称、索引或者是位地址。因此，你可以参看中断允许SFR中的EA（EA、IE.7或0AFH）位。SFR可控制的东西有：定时/计数器和UART的功能。中断源以及它们的优先级。这些被访问的寄存器在数据段中的字节和位是同一张指令表。表A所示SFR的存储图中指明了可寻址的位寄存器。IDATA空间某些8051家族成员，如8052在内部RAM中包含一个辅助128字节，存放在80H以上的单元。这个典型的RAM段被称为IDATA段。因为IDATA地址和SFR地址重叠，IDATARAM和SFR之间的地址冲突是通过分解被存取存储器的类型来解决，因为IDATA段只能通过间接寻址方式存取。XDATA空间8051存储空间为64K，代码段可用16根地址线寻址。这个典型空间被称为外部数据存储空间（简称XDATA段）。这个段通常由各种RAM（通常为SRAM）、I/O设备或外围设备组成，8051必须通过总线连接。这个段的读或写操作至少需两次循环处理，并且它的执行既要用到DPTR又要用到R0和R1。就DPTR来说，它通常要在执行读或写操作所要求的两个循环外再附加加载两个或更多循环处理地址。同样，在一个周期内除了利用存储器自身存取之外，至少要加载R0或R1。显而易见，XDATA段的典型操作很简单，通常最少需三个循环处理。因此，数据段常用来存储常用变量。如果8051不需要用总线执行任何I/O设备或者设计者希望当I/O设备通过总线存取时让RAM循环开、关，那么它可使这个段全部占满64KRAM。微机接口微机接口实现两种信息形式的交换。在计算机之外，由电子系统所处理以一种物理形式存在，但在程序中，它是用数字表示的。任一接口的功能都可分为以某种形式进行数据变换的一些操作，所以外部和内部形式的转换由许多步骤完成的。所示的情况为例加以说明，图中展示了微计算机和产生的信号和形式被系统的其他部分处理之前需要再次转换.举例来说，许多传感器具有电阻变化，这必须由一专门电路转换成电压。这种将传感器输出转换成电压信号，并与系统的其他电路相连接的过程，称为信号调理。信号调理部分将源自传感器的电压或电流信号范围转换用模拟－数字转换器变成数字形式的信号范围。一个模拟－数字转换器（ADC）用来将连续变化信号变成相应的数字量，这数字量可是可能的二进制数值中的一个固定值。如果传感器输出不是连续变化的，就不需要模拟－数字转换。这种情况下，信号调理单元必须将输入信号变换成为另一信号，也可直接与接口的下一部分，即微计算机本身的输入输出相连接。输入／输出单元将数字＂开／关＂电压信号转换成能通过系统总线传送到系统总线传送到计算机的信号。这里每一根线的状态，无论是＂开＂或是＂关＂，用相应的＂1＂或＂0＂表示。对于已经转换成数字形式的模拟输入量，内部表示中用1和0组成的排列形式形成与补转换量相对应的二进制数。从接口得到的原数值会受到接口电路设计的限制，而且常需要线性化和量程调整才能形成适合于在主程序中使用的数值。举例来说，接口可用于转换范围为－20ºC至50ºC的温度，而8位转换器所产生的数值会在范围0至255之间。显然，从程序员的观点，对温度进行直接的处理要比使用由ADC所产生的与一个给定温度相一致的值要容易。接口操作需要将控制信号在微机和接口之间进行传送。根据这些理由，通常使用子程序来监督接口的具体操作，并完成任何所需的量程调整和/或线性化。输出接口采用相似的形式，明显的差别在于信息流的方向相反;是从程序到外部世界。这种情况下，程序可称为输出程序，它监督接口的操作并完成数字-模拟转换器（DAC）所需数字的标定。该子程序依次送出信息给输出器件，产生相应的电信号，由DAC转换成模拟形式。最后，信号经调理（通常是放大）以形成适应于执行器操作的形式。数字接口电路在微机电路中使用的信号几乎总是太小而不能被直接地连到“外部世界”，因而必须用某种形式将其转换成更适宜的形式。接口电路部分的设计是使用微机的工程师所面临最重要的任务之一。我们已经了解到微机中，信息以离或散的位形式表示。当微机要与只有打开或关闭操作的设备相连时，这种数字形式是最有用的，这里每一位都可表示一个开关或执行器的状态。连接逻辑电路时，必须小心翼翼，以保证它们的逻辑电平和电流额定值是兼容的。由逻辑电路产生的输出电压通以拉出或灌入最大额定电流时，按最弱情况下数值所定义。这样VOH是当拉出最大额定“高”输出电流IOH时的允许最小“高”电压，而VOL,则是当灌入最大额定“低”输出电流IOL时允许最“低”电压。对逻辑输入也有相应的参数，规定最小输入电压为逻辑“高”状态VIH，以及最大输入电压为逻辑“低”状态VIL。对于输入接口，也许设计所面临的主要问题是电噪声，小噪声信号会引起系统工作不良，而大量的噪声会造成永久性损坏。设计者必须从一开始就清楚这些危险。有许多方法保护接口电路和微机不受各种各样噪声影响，下面是一些例子：1.使用光电隔离或变压器实现微机系统和外部器件之间的输入输出电信号隔离。2.用一低通滤器和施密特触发器排除高频噪声脉冲。3.用一对二极管以反向偏置于正常方向的形式连接至电源端，来保护过高的输入电压。对于输出接口，一个逻辑器件的参数VOH，VOL，IOH，和IOL往往太小而不能直接与负载相连，实践中必须在一个外部将电流和电压进行放大以驱动一个负载。现在尽管有一些类型的半导体器件可用于DC和AC的功率控制至若干千瓦，有两种基本方式将连至负载，并对其进行控制：串联连接和并联连接。对于串联连接，开关闭合时使电流渡过负载，而当并联连接时合上开关将使电流绕过负载。两种方式都可用于低功率电路中，但只有串联连接才能用于高功率电路，这是因为串联电阻R上要消耗功率。AT89C52的使用简介AT89C52带8K字节闪速存储器的8位单片机特性于80C51和80C52产品兼容8K字节编程闪速存储器寿命：1000次写/擦循环，数据保留时间：10年全静态工作：0H——24MHZ三级程序存储器锁定256×8位内部RAM三个16位定时器/计数器8个中断源可编程串行通道低功耗的闲置和掉电模式说明：AT89C52是一种带8K字节闪速可编程可擦除只读存储器（PEROM）的低电压、高性能CMOS8位为控制器。该器件采用ATMEL非易失存储器制造技术制造，与工业标准的80C51和80C52指令集和输出管脚相兼容。由于将多功能8位CPU和闪速存储器组合在单个芯片中，ATMEL的AT89C52是一种高效微控制器，为很多嵌入式控制系统提供