课程设计报告-四人抢答器

PAGE/课程设计报告课程设计报告设计题目四人抢答器专专业******班级******姓名******学号******指导教师******提交日期******摘要在许多比赛活动中,为了准确、公正、直观地判断出第一抢答者,通常设置一台抢答器。通过抢答器的数显,灯光和音响等手段指示出第一抢答者。同时还可以设置定时、记分犯规及奖惩等多种功能。本设计采用手动抢答的方式,有人抢答后,系统自动封锁其他人的抢答按钮,使其不能再抢答,从而实现抢答功能。数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出；用控制电路和主持人开关启动报警电路,以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能,构成扩展电路。经过模拟仿真,下载到开发板等工作后数字抢答器成型。关键字抢答电路定时电路报警电路时序控制目录摘要··········································································································1第1章概述·························································································3第2章课程设计任务及要求····························································42.1设计任务···············································································42.2设计要求···············································································4第3章系统设计··············································································53.1设计方案················································································53.2系统设计·················································································5结构框图及说明·························································5系统原理图及工作原理·············································63.3单元电路设计············································································7第4章软件仿真·················································································124.1仿真电路图··············································································124.2仿真过程··················································································124.3仿真结果··················································································14第5章安装调试·················································································145.1安装调试过程··········································································145.2故障分析··················································································15第6章心得体会··················································································16附录使用元件清单··············································································18参考文献·························································································18第1章概述随着社会的不断发展,人们的生活水平也在不断的提高人们不断要满足物质上的要求,同时对精神上的追求也在不断的提高,现在的社会是一个娱乐的社会。现在各电视台的活动和课外活动都很多。人们在参加活动的时候都对审判有很多的意见,所以为了比赛的准确和公正,就需要有仪器的辅佐。智力竞赛抢答器就是一种活泼的有趣的供人们娱乐的游戏装置,通过抢答方式不仅能引起参赛者和观众的兴趣,而且能够提高参赛者的敏捷性,同时我们在参与中能够增加一些生活常识和科学知识,因此,在许多比赛活动中为了准确,公正的进行每一场比赛,特别设置了一台具有显示第一抢答者并锁定、犯规警告等多种功能的抢答器,该设计针对各种要求设计出可供八名选手参赛使用的数字式竞赛抢答器,适用于各大中小电视台,学校等单位举行的智力竞赛。数字电路组成的数字系统工作可靠,精度较高,抗干扰能力很强,所以智力竞赛抢答器的设计就有数字电路来控制。第2章课程设计任务及要求2.1设计任务设计一个四位智力竞赛抢答器。准确地理解有关要求,独立完成系统设计,要求所设计的电路具有以下功能：〔1设计4组参赛的抢答器,每组设置一个抢答按钮。

〔2给节目主持人设置一个控制开关S,这个开关由主持人控制,进行清零和抢答使能。〔3抢答器具有锁存与显示功能。即选手按动按钮,锁存相应的编号,并在LED数码管上显示。〔4抢答器具有抢答计时功能,且一次抢答的时间由主持人设定〔如30秒。2.2设计要求1.分析设计任务,拟定多种设计方案,根据当时的制作条件,选定其中的一种方案绘制设计系统框图和设计流程。2.设计各部分单元电路图〔或VHDL描述。计算参数,选定元器件型号、确定数量,提出元件清单。3.安装、调试硬件电路,或制作以FPGA/CPLD为基础的专用集成电路芯片ASIC。4.电路测试、分析所要求的各项功能和指标,或对VHDL描述的电路作功能仿真和时序仿真,对ASIC芯片作脱机运行。5.运行制作的硬件电路,操作各项设计功能是否正常稳定,交验并演示所设计制作的电路装置6总结设计中各主要环节的资料,整理打印出规范的设计报告。第3章系统设计3.1设计方案该电路由抢答模块,锁存模块,定时模块,报警模块组成。抢答模块：由5个按钮组成,包括4个选手按钮和1个主持人按钮。当主持人按钮为低电平时,进行电路清零；为高电平时,选手开始抢答。当第一个选手抢到题后,发光二极管亮,显示其编号,并且扬声器响。锁存模块：当第一个选手抢到题后,若再有选手按按钮,不再识别其抢答信号。定时模块：主持人发出抢答信号后,电路进行自动计时,规定选手抢答在一定时间内完成。报警模块：与定时模块共同作用,如给定时间内无人抢答,扬声器响应报警,该题作废,进行下一题抢答。3.2系统设计结构框图及说明分析各项设计要求后,可绘制如下系统原理框图结构图说明第一信号鉴别电路是抢答器的关键电路,其任务是鉴别并锁存第一抢答者的信号,这类电路可以选用各种触发器、锁存器构成,也可用VHDL语言语言自己编写。其他模块的功能如前面所述,这里不再重复。系统原理图及工作原理工作原理：主持人按钮〔Q0拨向低电平,U1,U2的清零端CLR为低电平,实现电路清零,当主持人按钮拨向高电平,CLR高电平无效,此刻抢答开始,由于Q1~Q4原始状态为高电平,使得四输入与门输出为高电平,cp=‘1’,不能触发。当第一个人按下抢答按钮,输入低电平,四输入与门电平值由‘1’跳变为‘0’,此刻cp=‘0’,触发U1,使得U1输出端q=‘1’,此后无论其他选手再按按钮,cp=‘0’不变,实现对其他选手的锁存功能,U1输出q也一直保持为1,所以对于U2器件,只有一个脉冲触发,其输出q1~q4仅为s0~s1的第一个状态,在经U3器件进行转换后,由发光二极管输出〔点亮第一个抢答选手对应的发光二极管。而答题计时部分,由U2的输出端alm=‘1’使能U4,进行计时,计时输出由发光二极管显示。当在规定的时间没有答题结束,则蜂鸣器发出报警声。单元电路设计<1>.Catch元件器件生成所使用的VHDL语言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycatchisPort<cp:instd_logic;clr:instd_logic;q:outstd_logic>;endcatch;architectureBehavioralofcatchisbeginprocess<cp,clr>beginifclr='0'thenq<='0';elsifcp'eventandcp='0'thenq<='1';endif;endprocess;endBehavioral;器件描述：clr：clr=‘0’,清零,且q=‘0’；clr=‘cp：cp=‘1’,q=‘0’；cp=‘0’,q=<2>.Lock元件器件生成所使用的VHDL语言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitylockisPort<d1:instd_logic;d2:instd_logic;d3:instd_logic;d4:instd_logic;clk:instd_logic;clr:instd_logic;q1:outstd_logic;q2:outstd_logic;q3:outstd_logic;q4:outstd_logic;alm:outstd_logic>;endlock;architectureBehavioraloflockisbeginprocess<clk>beginifclr='0'then低电平有效q1<='0';q2<='0';q3<='0';q4<='0';alm<='0';elsifclk'eventandclk='1'thenq1<=d1;q2<=d2;q3<=d3;q4<=d4;alm<='1';endif;endprocess;endBehavioral;器件描述：clk：当clk=‘0’时,q1~q4=‘0’,alm=‘0’；当clk=‘1’时,q1<=d1;q2<=d2;q3<=d3;q4<=d4;d1~d4：d1~d4=s1~s4；<3>.ch41a元件器件生成所使用的VHDL语言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitych41aisPort<d1:instd_logic;d2:instd_logic;d3:instd_logic;d4:instd_logic;q:outstd_logic_vector<3downto0>>;endch41a;architectureBehavioralofch41aisbeginprocess<d1,d2,d3,d4>variabletmp:std_logic_vector<3downto0>;begintmp:=d1&d2&d3&d4;casetmpiswhen"0111"=>q<="0001";when"1011"=>q<="0010";when"1101"=>q<="0010";when"1110"=>q<="0100";whenothers=>q<="1111";endcase;endprocess;endBehavioral;器件描述：该器件主要实现d1~d4输入的转换功能,也就是将最原始的抢答输入进行转换,通过该器件,将原始抢答时刻s1~s4状态输出至发光二极管,也就最终实现谁先抢答,对应的发光二极管点亮。<4>.Count元件器件生成所使用的VHDL语言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycountisPort<clk:instd_logic;en:instd_logic;h:outstd_logic_vector<3downto0>;l:outstd_logic_vector<3downto0>;sound:outstd_logic>;endcount;architectureBehavioralofcountisbeginprocess<clk,en>variablehh,ll:std_logic_vector<3downto0>;beginifclk'eventandclk='1'thenifen='1'thenifll=0andhh=0thensound<='1';elsifll=0thenll:="1001";hh:=hh-1;elsell:=ll-1;endif;elsesound<='0';hh:="1001";ll:="1001";endif;endif;h<=hh;l<=ll;endprocess;endBehavioral;器件描述：该器件主要是一个计时器件,计时可以由主持人自己设定,h为高位,l为地位,由alm输入到使能端使能,开始计时,当外部来一个时钟脉冲,自减一,当倒计时结束时,sound=‘1’,使得报警器响。第4章软件仿真4.1仿真电路图4.2仿真过程编译无误之后,将以上原理图生成VHDL语言,继而生成VHDTEST文件,将激励信号输入VHDTEST文件,进行仿真。激励信号：s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s3<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s2<='0';waitfor2ns;s1<='0';waitfor2ns;s3<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s3<='0';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s4<='0';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s3<='0';waitfor5ns;4.3仿真结果仿真波形如下：经观察检测,仿真结果符合预定要求。第5章安装调试5.1安装调试过程根据要求,下载原理图设计如下经计算,选用两个256分频,一个16分频,即1M分频,获得所需脉冲；将count的sound引脚接蜂鸣器,实现报警；将Ch41a及Count的输出通过J4B_4S接到8个LED上,其中,前4个用来显示抢到题的选手序号,后4个用来显示时间,实现答题倒计时。5.2故障分析下载过程中有以下问题〔1原理图生成VHDL语言时,出现错误,经检查,原因主要有：部分输出管脚为空；端口未定义属性。〔2蜂鸣器声音刺耳经查找资料,这是频率选择不合适的问题,〔3未答题前