至60宽范输入同步脉宽调制pwm降压控制器

TPS40170-ZHCS826A–JANUARY2012–REVISEDMARCH4.5V至60V宽范输入同步脉宽调制 )降压控制查询样品:TPS40170-特 应用范 负载点(POL)模 ––40°C+125

TPS40170-Q1是一款功能齐全的同步 器件充电器件模型(CDM)ESD分类等级 4.5V至60V宽泛输入电 600mV基准电压，精度 kHz至600kHz之间进行编程可编程欠压闭锁(UVLO)与磁 100kHz与600kHz间的可编程编程频 具有集成热补偿的低侧场效应晶体(FET)传感过流 式下实现系统关断。控制器支持预偏置输出，提供一保护和高侧FET传感短路保护 个开漏电源良好(PGOOD)信号，并支持闭环软启动、 输出电 8V3.3V(LDO203.5mmx4.5mm

TPS40170-Q1 工作的下游控制器，可与主器件同相或180°异相同±30%以内与Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.©2012,TexasInstrumentsNexFETisatrademarkof©2012,TexasInstrumentsPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoes EnglishDataSheet:necessarilyincludetestingofall 2VIN3BOOT4HDRV5SW6VBP7LDRV8PGND9AGND ILIM12 ThisintegratedcircuitcanbedamagedbyESD.TexasInstruments mendsthatallintegratedcircuitsbehandledwithappropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.ORDERINGTRANSPORTDEVICE–40°CtoTapeandForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthis,orseetheTIwebsiteatPackagedrawings,thermaldata,andsymbolizationareavailable UMoveroperatingfree-airtemperaturerange(unlessotherwiseInputVVSW+OutputVBOOT-SW,HDRV-SW(differentialfromBOOTorHDRVtoSW)VBP,LDRV,COMP,RT,ENABLE,PGOOD,VDD,FB,TRK,SS,AGND-PGND,PGND-PowerPADtoAGND(mustbeelectricallyconnectedexternaltodevice)0ElectrostaticdischargeHuman-bodymodel(HBM)AEC-Q100ClassificationLevelH1CCharged-devicemodel(CDM)AEC-Q100ClassificationLevelC3BVAmbienttemperatureStorage(1)StressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseincludedunder mendedOperatingConditionsisnotimplied.Exposuretoabsolute-um-ratedconditionsforextendedperiodsoftimemayaffectdevicereliability.THERMALTHERMALTPS40170-RGY(20Junction-to-ambientthermalJunction-to-case(top)thermalJunction-to-boardthermalJunction-to-topcharacterizationJunction-to-boardcharacterizationJunction-to-case(bottom)thermal有关传统和新的热度量的信息，请参阅IC封装热度量应用报告SPRA953MENDEDOPERATINGoveroperatingfree-airtemperaturerange(unlessotherwiseInputVELECTRICALThesespecificationsapplyfor–40ºC≤TA≤+125ºC,VVIN=12V,unlessotherwiseTESTINPUTInputvoltageVShutdownVENABLE<1001Operatingcurrent,driversnotVENABLE≥2V,fSW=300ENABLEpinvoltagetodisabletheENABLEpinvoltagetoenabletheENABLEpinsource8-VAND3.3-V8-VregulatoroutputVENABLE≥2V,8.2V<VVIN≤60V,0mA<IIN<20mAV8-Vregulatordropoutvoltage,4.5<VVIN≤8.2V,VEN≥2V,IIN=10mA3.3-VregulatoroutputVENABLE≥2V,4.5V<VVIN≤60V,0mA<IIN<5mAVFIXEDANDPROGRAMMABLEProgrammableUVLOONvoltage(atUVLOVENABLE≥2HysteresiscurrentoutofUVLOVENABLE≥2V,UVLOpin>5VBPturnonVENABLE≥2V,UVLOpin>VVBPturnoffVBPUVLOHysteresisReferencevoltage(+inputoftheerrorTJ=25°C,4.5V<VVIN≤60–40°C≤TJ≤125ºC,4.5V<VVIN≤60 SwitchingRangeRRT=100kΩ,4.5V<VVIN≤60RRT=31.6kΩ,4.5V<VVIN≤60RRT=14.3kΩ,4.5V<VVIN≤60Valley1V gain(VVIN/VRAMP)4.5V<VVIN≤60ANDDUTYCYCLE MinimumcontrolledVVIN=4.5V,fSW=300VVIN=12V,fSW=300VVIN=60V,fSW=300MinimumOFFVVIN=12V,fSW=300DM(1)umdutyfSW=100kHz,4.5V<VVIN≤60FSW=300kHz,4.5V<VVIN≤60fSW=600kHz,4.5V<VVIN≤60NotproductionELECTRICALELECTRICALCHARACTERISTICSThesespecificationsapplyfor–40ºC≤TA≤+125ºC,VVIN=12V,unlessotherwiseTESTERRORGBWPGainbandwidth7Open-loopInputbiasOutputsourceVVFB=02OutputsinkVVFB=12PROGRAMMABLESOFTSoft-startsourcecurrentatVSS<0.5VSS=0.25Soft-startsourcecurrentatVSS>0.5VSS=1.5Soft-startsinkVSS=1.5SSpinHIGHvoltageduringfault(OCorthermal)resettimingVSSpinLOWvoltageduringfault(OCorthermal)resettimingSSpinvoltageduringsteady-VInitialoffsetvoltagefromSSpintoerroramplifierinput)RangeofTRKwhichoverrides4.5V<VIN≤600SYNCHRONIZATIONM/Spinvoltageinmaster VM/Spinvoltageinslave0ºVM/Spinvoltageinslave180º0VSYNCpinpulldown8SYNCpininputhigh-voltageM/Sconfiguredasslave-0º2VSYNCpininputlow-voltageVslave-MinimumSYNChighpulseMinimumSYNClowpulseGATEHigh-sidedriverpullup4ΩHigh-sidedriverpulldownCLOAD=2.2nF,IDRV=300mA,TA=–40°C4ΩLow-sidedriverpullup4ΩLow-sidedriverpulldownΩtNON-TimedelaybetweenHDRVfallandLDRVCLOAD=2.2VHDRV=2V,VLDRV=2tNON-TimedelaybetweenHDRVriseandLDRVOVERCURRENTPROTECTION(LOW-SIDEMOSFETILIMpinsource4.5V<VIN<60V,TA=94.5V<VIN<60V,TA=–40°Cto7ILIMpinsourcecurrentduringsoft-4.5V<VIN<60V,TA=4.5V<VIN<60V,TA=–40°Cto7IILIM,TemperaturecoefficientofILIM4.5V<VIN<60VILI(2)ILIMpinvoltageoperating4.5V<VIN<60Overcurrentprotectionthreshold(voltageacrosslow-sideFETfordetectingovercurrent)RILIM=10kΩ,IILIM=10µA(VILIM=100mV)SHORTCIRCUITPROTECTIONHIGH-SIDEMOSFETLDRV umvoltageduringRLDRV=MultiplierfactortosettheSCPbasedonRLDRV=10RLDRV=levelsettingatheILIMRLDRV=20NotproductionTESTTHERMALTSD,setThermalshutdownsetThermalshutdownreset4.5V<VVIN<60ThermalshutdownPOWERFBpinvoltageupperlimitforpowerFBpinvoltagelowerlimitforpowerPowergoodhysteresisvoltageatFB4.5V<VVIN<60VPGOODpinvoltagewhenFBpinvoltageVOVor<VUV,IPGD=2PGOODpinvoltagewhendevicepowerisVVINisopen,10-kΩtoVEXT=51VBOOT BootstrapdiodeforwardI=20VRBOOT-DischargeresistorfromBOOTto1NotproductionDEVICE(Top 21213456789 PIN9—ogsignalground.ThispinmustbeelectricallyconnectedtopowergroundPGNDOBoot-capacitornodeforhigh-sideFETgatedriver.Thebootcapacitorisconnectedfromthispinto8OOutputoftheinternalerroramplifier.ThefeedbackloopcompensationnetworkisconnectedfromthispintotheFBpin.1IThispinmustbehighforthedevicetobeenabled.Ifthispinispulledlow,thedeviceisputinalow-power-consumptionshutdownmode.7INegativeinputtotheerroramplifier.Theoutputvoltageisfedbacktothispinthrougharesistor-dividerOGate-driveroutputforthehigh-sideIAresistorfromthispintoPGNDsetstheovercurrentlimit.Thispinprovidessourcecurrentusedfortheovercurrent-protectionthresholdsetting.OGatedriveroutputforthelow-sideFET.Also,aresistorfromthispintoPGNDsetsthemultiplierfactortodeterminetheshort-circuitcurrentlimit.Ifnoresistorispresent,themultiplierdefaultsto7timestheILIMpinvoltage.3IMaster-orslave-modeselectorpinforfrequencysynchronization.ThispinmustbetiedtoVINformastermode.Intheslavemode,thispinmustbetiedtoAGNDorleftfloating.IfthepinistiedtoAGND,thedevicesynchronizeswitha180°phaseshift.Ifthepinisleftfloating,thedevicesynchronizeswitha0°phaseshift.—Powerground.ThispinmustexternallyconnecttotheAGNDatasingleOPower-goodindicator.Thispinisanopen-drainoutputpin,anda10-kΩpullupresistorisbeconnectedbetweenthispinandVDD.mended4IAresistorfromthispintoAGNDsetstheoscillatorfrequency.Evenifoperatinginslavemode,itisrequiredtohavearesistoratthispintosetthefree-runningswitchingfrequency.5ISoft-start.AcapacitormustbeconnectedfromthispintoAGND.Thecapacitorvaluesetsthesoft-startIThispinmustconnecttotheswitchingnodeofthesynchronousbuckconverter.Thehigh-sideandlow-sideFETcurrentsensingarealsodonefromthisnode.2Synchronization.Thisisabidirectionalpinusedforfrequencysynchronization.Inthemastermode,itistheSYNCoutputpin.Intheslavemode,itisaSYNCinputpin.Ifunused,thispincanbeleftopen. ITracking.Externalsignalatthispinisusedforoutputvoltagetracking.Thispingoesdirectlytotheinternalerroramplifierasapositivereference.ThelesserofthevoltagesbetweenVTRKandtheinternal600-mVreferencesetstheoutputvoltage.Ifnotused,thispinshouldbepulleduptoVDD.PINFUNCTIONSIUndervoltagelockout.AresistordivideronthispinfromVINtoAGNDcanbeusedtosettheUVLOO8-Vregulatedoutputforgatedriver.Aceramiccapacitorwithavaluebetween1µFand10µFmustbeconnectedfromthispintoPGNDO3.3-Vregulatedoutput.Aceramicbypasscapacitorwithavaluebetween0.1µFand1µFmustbeconnectedbetweenthispinandtheAGNDpinandplacedcloselytothispin.IInputvoltageforthecontroller,whichisalsotheinputvoltageforthedc-dcconverter.A1-µFbypasscapacitorfromthispintoAGNDmustbeaddedandplacedclosedtoVIN.DEVICEBLOCK

3.3-3.3-Over-Soft-

UDG-TYPICALReferenceReferenceVoltage−40−25−10 203550658095110

VINVIN=4.5VVIN=24VVIN=60VfSW=100SwitchingSwitchingFrequency−40−25−10 203550

8095110Temperature Figure1.ReferenceVoltagevsJunction Figure2.SwitchingFrequencyvsJunction(fSW=100VINVIN=4.5VVIN=24VVIN=60VfSW=300SwitchingSwitchingFrequency−40−25−10 203550

8095110

VINVIN=4.5VVIN=24VVIN=60VfSW=600SwitchingSwitchingFrequency−40−25−10 203550658095110JunctionTemperature Figure3.SwitchingFrequencyvsJunctionTemperature Figure4.SwitchingFrequencyvsJunctionTemperature(fSW=300kHz) (fSW=600kHz)VINVIN=12ShutdownShutdownCurrent−40−25−10 203550658095110Temperature

VINVIN=12VfSW=300kHzOperatingOperatingCurrent−40−25−10 203550658095110JunctionTemperatureFigure5.ShutdownCurrentvsJunction Figure6.OperatingCurrentvsJunctionTYPICALTYPICALCHARACTERISTICSUVLOUVLOOnVoltage

UVLOHysteresisUVLOHysteresisCurrent−40−25−10 203550658095110JunctionTemperature

−40−25−10 203550658095110JunctionTemperatureFigure7.UVLOOnVoltagevsJunction Figure8.UVLOHysteresisCurrentvsVBPVBPTurn−OnVoltage−40−25−10 203550658095110JunctionTemperatureFigure9.VBPTurnonVoltagevsJunction

VBPUVLOVBPUVLOHysteresisVoltage−40−25−10 203550658095110JunctionTemperatureFigure10.VBPUVLOHysteresisVSS>VSS>0.5VSS<0.5Soft−StartSoft−StartSourceCurrent

Soft−StartSoft−StartSourceCurrent

−40−25−10 203550658095110JunctionTemperature

−40−25−10 203550658095110JunctionTemperatureFigure11.Soft-StartSourceCurrentvsJunction Figure12.Soft-StartSourceCurrentvsJunctionTemperature(VSS>0.5V) Temperature(VSS<0.5V)ILIMILIMSourceCurrent

Soft−StartInitialSoft−StartInitialOffsetVoltage−40−25−10 203550658095110JunctionTemperature

−40−25−10 203550658095110JunctionTemperatureFigure13.ILIMSourceCurrentvsJunction Figure14.Soft-StartInitialOffsetVoltagevsPowerPowerGoodThresholdVoltage−40−25−10 203550658095110JunctionTemperatureFigure15.VOV/VUVPowerGoodThresholdAPPLICATIONFUNCTIONALTheTPS40170-Q1isasynchronous buckcontrollerthatacceptsawiderangeofinputvoltagesfrom4.5Vto60Vandfeaturesvoltage-modecontrolwithinput-voltagefeed-forwardcompensation.Theswitchingfrequencyisprogrammablefrom100kHzto600kHz.TheTPS40170-Q1hasacompletesetofsystemprotectionssuchasprogrammableUVLO,programmableovercurrentprotection(OCP),selectableshort-circuitprotection(SCP),andthermalshutdown.TheENABLEpinallowsforsystemshutdowninalow-current(1-µAtypical)mode.Thecontrollersupportspre-biasedoutputs,providesanopen-drainPGOODsignal,andhasclosed-loopprogrammablesoft-start,output-voltagetracking,andadaptivedead-timecontrol.TheTPS40170-Q1providesaccurateoutputvoltageregulationwithin1%Additionally,thecontrollerimplementsanovelschemeofbidirectionalsynchronizationwithonecontrolleractingasthemasterandotherdownstreamcontrollersactingasslaves,synchronizedtothemasterin-phaseor180°out-of-phase.Slavecontrollerscanbesynchronizedtoanexternalclockwithin±30%oftheinternalswitchingfrequency.LDOLinearRegulatorsandTheTPS40170-Q1hastwointernallow-dropout(LDO)linearregulators.OnehasanominaloutputvoltageofVVBPandispresentattheVBPpin.Thisisthevoltagethatismainlyusedforthegate-driveroutput.TheotherlinearregulatorhasanoutputvoltageofVVDDandispresentattheVDDpin.Thisvoltagecanbeusedinexternallow-currentlogiccircuitry.TheumallowablecurrentdrawnfromtheVDDpinmustnotexceed5mA.TheTPS40170-Q1hasadedicateddevice-enablepin(ENABLE).Thissimplifiesuser-levelinterfacedesignbecausenomultiplexedfunctionsexist.IftheENABLEpinoftheTPS40170-Q1ishigherthanVEN,thentheLDOregulatorsareenabled.ToensurethattheLDOregulatorsaredisabled,theENABLEpinmustbepulledbelowVDIS.BypullingtheENABLEpinbelowVDIS,thedeviceiscompleydisabledandthecurrentconsumptionisverylow(nominally,1µA).BothLDOregulatorsareactivelydischargedwhentheENABLEpinispulledbelowVDIS.AfunctionallyequivalentcircuittotheenablecircuitryontheTPS40170-Q1isshowninFigure16.AlwaysISD=1UDGFigure16.TPS40170-Q1ENABLEFunctionalTheENABLEpinmustnotbeallowedtofloat.IftheENABLEfunctionisnotneededforthedesign,thenitissuggestedthattheENABLEpinbepulleduptoVINbyahigh-valueresistor,ensuringthatthecurrentintotheENABLEpindoesnotexceed10µA.Ifitisnotpossibletomeetthisclampcurrentrequirement,thenitissuggestedthataresistordividerfromVINtoGNDbeusedtoconnecttoENABLEpin.TheresistordividershouldbesuchthattheENABLEpinishigherthanVENandlowerthan8V.Toavoidpotentialerroneousbehavioroftheenablefunction,theENABLEsignalappliedmusthaveaminimumslewrateof20V/s.InputUndervoltageLockoutTheTPS40170-Q1hasbothfixedandprogrammableinputundervoltagelockout(UVLO).InorderforthedevicetoturnON,allofthefollowingconditionsmustbemet:TheENABLEpinvoltagemustbegreaterthanTheVBPvoltage(atVBPpin)mustbegreaterthanTheUVLOpinmustbegreaterthanInorderforthedevicetoturnOFF,anyoneofthefollowingconditionsmustbeTheENABLEpinvoltagemustbelessthanTheVBPvoltage(attheVBPpin)mustbelessthanTheUVLOpinmustbelessthanProgrammingtheinputUVLOcanbe plishedusingtheUVLOpin.Aresistordividerfromtheinputvoltage(VINpin)toGNDsetstheUVLOlevel.OncetheinputvoltagereachesavaluethatmeetstheVUVLOlevelattheUVLOpin,thenasmallhysteresiscurrent,IUVLOattheUVLOpinisswitchedin.TheprogrammableUVLOfunctionisshowninFigure17.++91UDGFigure17.UVLOFunctionalBlockEquationsforProgrammingtheInputComponentsR1andR2representexternalresistorsforprogrammingUVLOandhysteresis;theirvaluescanbecalculatedinEquation1andEquation2,respectively.VONR1

R2R1VONVUVLOVONisthedesiredturnonvoltageoftheVOFFisthedesiredturnoffvoltagefortheIUVLOisthehysteresiscurrentgeneratedbythedevice,5µAVUVLOistheUVLOpinthresholdvoltage,0.9V IftheUVLOpinisconnectedtoavoltagegreaterthan0.9V,theprogrammableUVLOisdisabledandthedevicedefaultstoaninternalUVLO(VVBP(on)andVVBP(off)).Forexample,theUVLOpincanbeconnectedtoVDDortheVBPpintodisabletheprogrammableUVLOA1-nFceramicbypasscapacitormustbeconnectedbetweentheUVLOpinandOscillatorandVoltageFeed-TPS40170-Q1implementsanoscillatorwithinput-voltagefeed-forwardcompensationthatenablesinstantresponsetoinputvoltagechanges.Figure18showstheoscillatortimingdiagramfortheTPS40170-Q1.TheresistorfromtheRTpintoGNDsetsthefree-runningoscillatorfrequency.VoltageVRTontheRTpinismadeproportionaltotheinputvoltage(seeEquation3).VRTKK= TheresistorattheRTpinsetsthecurrentintheRTpin.Theproportionalcurrentchargesaninternal100-pFoscillatorcapacitor.TherampvoltageonthiscapacitoriscomparedwiththeRTpinvoltage,VRT.OncetherampvoltagereachesVRT,theoscillatorcapacitorisdischarged.Therampthatisgeneratedbytheoscillator(whichisproportionaltotheinputvoltage)actsasvoltagefeed-forwardramptobeusedinthecomparator.Thetimebetweenthestartofthedischargingoscillatorcapacitorandthestartofthenextchargingcycleisfixedat170ns(typical).Duringthefixeddischargetime,theoutputismaintainedasOFF.ThisistheminimumOFF-timeoftheoutput.tFigure18.Feed-ForwardOscillatorTimingCalculatingthe 104RRT fSW

UDG-fSWistheswitchingfrequencyinRRTistheresistorconnectedfromRTpintoGNDin Theswitchingfrequencycanbeadjustedbetween100kHzand600kHz.The switchingfrequencybeforeskippulsesisdeterminedbytheinputvoltage,outputvoltage,FETs,DCRoftheinductor,andtheminimumon-timeoftheTPS40170-Q1.UseEquation5todeterminethe umswitchingfrequency.For furtherdetails,seeapplicationnoteSLYT293.VOUTminIOUTminRDS2RLOADfSWmax

tONminVINmaxIOUTminRDS1RDS2fSW(max)istheumswitchingVOUT(min)istheminimumoutputVIN(max)istheuminputIOUT(min)istheminimumoutputRDS1isthehigh-sideFETRDS2isthelow-sideFETRLOADistheinductorseries OvercurrentProtectionandShort-CircuitProtection(OCPandTheTPS40170-Q1hasthecapabilitytosetatwo-levelovercurrentprotection.Thefirstlevelofovercurrentprotection(OCP)isthenormaloverloadsettingbasedonlow-sideMOSFETvoltagesensing.Thesecondlevelofprotectionistheheavyoverloadsetting,suchasshort-circuitbased,onthehigh-sideMOSFETvoltagesensing.Thisprotectiontakeseffectimmediay.Thesecondlevelistermedshort-circuitprotection(SCP).TheOCPlevelissetbytheILIMpinvoltage.Acurrent(IILIM)issourcedintotheILIMpinfromwhicharesistorRILIMisconnectedtoGND.ResistorRILIMsetsthefirstlevelofovercurrentlimit.TheOCPisbasedonthelow-sideFETvoltageattheswitch-node(SWpin)whenLDRVisONafterablankingtime,whichistheproductofinductorcurrentandlow-sideFETturnonRDS(on).ThevoltageisinvertedandcomparedtoILIMpinvoltage.IfitisgreaterthantheILIMpinvoltage,thena3-bitcounterinsidethedeviceincrementsthefault-countby1atthestartofthenextswitchingcycle.Alternatively,ifitislessthantheILIMpinvoltage,thenthecounterinsidethedevicedecrementsthefault-countby1.Whenthefault-countreaches7,anovercurrentfault(OC_FAULT)isdeclaredandboththeHDRVandLDRVareturnedOFF.ResistorRILIMcanbecalculatedbyEquation6. IOCRDS(on)IOC TheSCPlevelissetbyamultipleoftheILIMpinvoltage.Themultiplierhasthreediscretevalues,3,7,or15times,whichcanbeselectedbychoosinga10-kΩ,open-circuit,or20-kΩresistor,respectively,fromtheLDRVpintoGND.ThismultiplierAOCinformationistranslatedduringthetCALtime,whichstartsaftertheenableandUVLOconditionsaremet.TheSCPisbasedonsensingthehigh-sideFETvoltagedropfromVVINtoVSWwhenHDRVisONafterablankingtime,whichisproductofinductorcurrentandhigh-sideFETturnon RDS(on).ThevoltageiscomparedtotheproductofthemultiplierandtheILIMpinvoltage.Ifthevoltageexceedstheproduct,thenthefault-countisimmediaysetto7andtheOC_FAULTisdeclared.HDRVisterminatedimmediaywithoutwaitingforthedutycycletoend.WhenanOC_FAULTisdeclared,boththeHDRVandLDRVareturnedOFF.Theappropriatemultiplier(A),canbeselectedusingEquation7.AISCIOCHDRV(Ax3Bit+LDRVHDRV(Ax3Bit+LDRV+OC++A37Figure19.OCPandSCPProtectionFunctionalBlock

UDGBothOCPandSCParebasedonlow-sideandhigh-sideMOSFETvoltagesensingattheSWnode.ExcessiveringingontheSWnodecanhaveanegativeimpactontheaccuracyofOCPandSCP.AddinganR-CsnubberfromtheSWnodetoGNDhelpsminimizethepotentialimpact.Soft-StartandFault-AcapacitorfromtheSSpintoGNDdefinestheSStime,tSS.TheTPS40170-Q1entersintosoft-startimmediayaftercompletionoftheovercurrentcalibration.TheSSpingoesthroughtheinternallevel-shiftercircuitofthedevicebeforereachingoneofthepositiveinputsoftheerroramplifier.TheSSpinmustreachapproximay0.65Vbeforetheinputtotheerroramplifierbeginstoriseabove0V.TochargetheSSpinfrom0Vto0.65Vfaster,anextrachargingcurrent(40.4µA,typ.)isswitched-intotheSSpinatthebeginningofthesoft-startinadditiontothenormalchargingcurrent(11.6µA,typ.).AstheSScapacitorreaches0.5V,theextrachargingcurrentisturnedoffandonlythenormalchargingcurrentremains.Figure20showsthesoft-startfunctionblock.40.411.60.875 ++SoftStartR1Figure20.Soft-StartSchematicAstheSSpinvoltageapproaches0.65V,thepositiveinputtotheerroramplifierbeginstorise(seeFigure21).Theoutputoftheerroramplifier(theCOMPpin)startsrising.TherateofriseoftheCOMPvoltageismainlylimitedbythefeedback-loopcompensationnetwork.OnceVCOMPreachestheVvalleyoftheramp,theswitchingbegins.TheoutputisregulatedtotheerroramplifierinputthroughtheFBpininthefeedbackloop.OncetheFBpinreachesthe600-mVreferencevoltage,thefeedbacknodeisregulatedtothereferencevoltage,VREF.TheSSpincontinuestoriseandisclampedtoVDD.TheSSpinisdischargedthroughaninternalswitchduringthefollowingInput(VIN)undervoltagelockoutUVLOpinlessthanOvercurrentprotectioncalibrationtimeVBPlessthanthresholdvoltageBecauseitisdischargedthroughaninternalswitch,thedischargingtimeisrelativelyfastcomparedwiththedischargingtimeduringthefaultrestart,whichisdiscussedintheSoft-startDuringOvercurrentFaultsection.ClampedatClampedat1.1VREF=0.60.650.5ReferringtoFigure

tFigure21.Soft-StartWaveforms

UDG-VREFdominatesthepositiveinputoftheerrorSS_EAMPdominatesthepositiveinputoftheerrorFor0<VSS_EAMP<

VSS(EAMP)

R1 ForVSS_EAMP>

R1VOUT

Soft-StartDuringOvercurrentPersistentFAULTFAULT2.5300Thesoft-startblockalsohasaroletocontrolthefault-logictiming.Ifanovercurrentfault(OC_FAULT)isdeclared,thesoft-startcapacitorisdischargedinternallythroughthedevicebyasmallcurrentISS(sink)(1.05µA,typ.).OncetheSSpincapacitorisdischargedtobelowVSS(flt,low)(300mV,typ.),thesoft-startcapacitorbeginschargingagain.Ifthefaultispersistent,afaultisdeclaredwhichisdeterminedbyPersistentFAULTFAULT2.5300

tFigure22.OvercurrentFaultRestart

UDG-ForthefeedbacktoberegulatedtotheSS_EAMPvoltage,theTRKpinmustbepulledhighdirectlyorthrougharesistortoVDD.EquationsforSoft-StartandRestartThesoft-starttime(tSS)isdefinedasthetimetakenfortheinternalSS_EAMPnodetogofrom0Vtothe0.6-VVREFvoltage.SS_EAMPstartsrisingastheSSpingoesbeyond0.65V.TheoffsetvoltagebetweenSSandSS_EAMPstartsincreasingastheSSpinvoltagestartsrising.Figure21showsthattheSStimecanbedefinedasthetimetakenfortheSSpinvoltagetochangeby1.05V(seeEquation10).

Therestarttime(tRS)isdefinedinEquation11asthetimetakenforthesoft-startcapacitor(CSS)todischargefrom2.5Vto0.3Vandtothenrechargeupto2.5V.tRS2.28CSSisthesoft-startcapacitanceintSSisthesoft-starttimeintRSistherestarttimein Duringsoft-start(VSS<2.5V),theovercurrentprotectionlimitis1.5timesthenormalovercurrentprotectionlimit.Thisallowsahigheroutputcapacitancetochargefullywithoutactivatingovercurrentprotection.OvertemperatureFigure23showstheovertemperatureprotectionscheme.IfthejunctiontemperatureofthedevicereachesthethermalshutdownlimitoftSD(set)(165°C,typ)andSSchargingiscompleted,anovertemperatureFAULTisdeclared.Thesoft-startcapacitorbeginstobedischarged.Duringsoft-startdischargingperiod,the switchingisterminated;therefore,bothHDRVandLDRVaredrivenlow,turningoffbothMOSFETs.Persistent2.5300mV Thesoft-startcapacitorbeginstochargeandanovertemperaturefaultisresetwheneverthesoft-startcapacitorisdischargedbelowVSS(flt,low)(300mV,typ.).Duringeachrestartcycle,switchingisturnedon.WhenSSisfullycharged,switchingisterminated.Theserestartsrepeatuntilthetemperatureofthedevicehasfallenbelowthethermalresetlevel,tSD(reset)(135°Ctyp).switchingcontinuesPersistent2.5300mV

tFigure23.OvertemperatureFaultRestart

UDG-Thesoft-starttimingduringanovertemperaturefaultisthesameasthesoft-starttimingduringanovercurrentfault.SeetheEquationsforSoft-StartandRestartTimesection.FrequencyTheTPS40170-Q1hasthreeMastermode:Inthismode,themaster-orslave-selectorpin,(M/S)isconnectedtoVIN.TheSYNCpinemitsastreamofpulsesatthesamefrequencyastheswitchingfrequency.ThepulsestreamattheSYNCpinisof50%dutycycleandthesameamplitudeasVVBP.Also,thefallingedgeofthevoltageonSYNCpinissynchronizedwiththerisingedgeofHDRV.Slave–180°mode:Inthismode,theM/SpinisconnectedtoGND.TheSYNCpinoftheTPS40170-Q1acceptsasynchronizationclocksignal,andHDRVissynchronizedwiththerisingedgeofthe ingsynchronizationSlave–0°mode:Inthismode,theM/Spinisleftopen.TheSYNCpinoftheTPS40170-Q1acceptsasynchronizationclocksignal,andHDRVissynchronizedwiththefallingedgeofthe ingsynchronizationThetwoslavemodescanbesynchronizedtoanexternalclockthroughtheSYNCpin.TheyareshowninFigure24.Thesynchronizationfrequencyshouldbewithin±30%ofitsprogrammedfree-runningfrequency.MasterMode(SYNCasanoutputtSlave180Mode(SYNCasaninput

tSlave0Mode(SYNCasaninput

t

UDG-Figure24.FrequencySynchronizationWaveformsinDifferentTPS40170-Q1providesasmoothtransitionfortheSYNCclock-signallossinslavemode.Inslavemode,asynchronizationclocksignalisprovidedexternallythroughtheSYNCpintothedevice.TheswitchingfrequencyissynchronizedtotheexternalSYNCclocksignal.Ifforsomereasontheexternalclocksignalismissing,thedeviceswitchingfrequencyisautomaticallyoverriddenbyatransitionfrequencywhichis0.7timesitsprogrammedfree-runningfrequency.Thistransitiontimeisapproximay20μs.Afterthat,thedeviceswitchingfrequencyischangedtoitsprogrammedfree-runningfrequency.Figure25showsthisprocess.

SYNCclockpulseSynchronizedfS=SYNCclock

20-stransitiondurationfS=0.7xrunningfrequency

FreerunningfS=freerunningUDG-Figure25.TransitionforSYNCClockSignalMissing(forSlave–180ºWhenthedeviceisoperatinginthemastermodewithdutyratioaround50%,jitteringmayoccur.AlwaysconfigurethedeviceintotheslavemodebyeitherconnectingtheM/SpintoGNDorleavingitfloatingifmastermodeisnotused.WhentheexternalSYNCclocksignalisusedforsynchronization,limittheumslewrateoftheclocksignalto10V/µstoavoidpotentialjittering,andconnecttheSYNCpintotheexternalclocksignalviaa5-kΩresistor.TheTRKpinisusedforoutputvoltagetracking.TheoutputvoltageisregulatedsothattheFBpinequalsthelowestoftheinternalreferencevoltage(VREF)orthelevel-shiftedSSpinvoltage(SSEAMP)ortheTRKpinvoltage.OncetheTRKpingoesabovethereferencevoltage,thentheoutputvoltageisnolongererned