2023年VHDL程序练习题含答案

VHDL程序填空题(一)在下面横线上填上合适的VHDL关键词，完毕2选1多路选择器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;1MUX21ISPORT(SEL:INSTD_LOGIC;A,B:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDMUX21;2BHVOFMUX21ISBEGINQ<=AWHENSEL=’1’ELSEB;ENDBHV;(二)在下面横线上填上合适的语句，完毕BCD-7段LED显示译码器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYBCD_7SEGISPORT(BCD_LED:INSTD_LOGIC_VECTOR(3DOWNTO0);LEDSEG:OUTSTD_LOGIC_VECTOR(6DOWNTO0)); ENDBCD_7SEG; ARCHITECTUREBEHAVIOROFBCD_7SEGISBEGINPROCESS(BCD_LED)3IFBCD_LED="0000"THENLEDSEG<="0111111"; ELSIFBCD_LED="0001"THENLEDSEG<="0000110"; ELSIFBCD_LED="0010"THENLEDSEG<=4; ELSIFBCD_LED="0011"THENLEDSEG<="1001111"; ELSIFBCD_LED="0100"THENLEDSEG<="1100110"; ELSIFBCD_LED="0101"THENLEDSEG<="1101101"; ELSIFBCD_LED="0110"THENLEDSEG<="1111101"; ELSIFBCD_LED="0111"THENLEDSEG<="0000111"; ELSIFBCD_LED="1000"THENLEDSEG<="1111111"; ELSIFBCD_LED="1001"THENLEDSEG<="1101111"; ELSELEDSEG<=5; ENDIF;ENDPROCESS;ENDBEHAVIOR;(三)在下面横线上填上合适的语句，完毕数据选择器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX16ISPORT(D0,D1,D2,D3:INSTD_LOGIC_VECTOR(15DOWNTO0); SEL:INSTD_LOGIC_VECTOR(6DOWNTO0); Y:OUTSTD_LOGIC_VECTOR(15DOWNTO0));END;ARCHITECTUREONEOFMUX16ISBEGINWITH7SELECT Y<=D0WHEN"00", D1WHEN"01", D2WHEN"10", D3WHEN8;END;(四)在下面横线上填上合适的语句，完毕JK触发器的设计。说明：设计一个异步复位/置位JK触发器，其真值表如下： INPUTOUTPUTPSETCLRCLKJKQ01XXX110XXX000XXX不定11上升沿01011上升沿10111上升沿11翻转11上升沿00保持LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJKFF1ISPORT(PSET,CLR,CLK,J,K :INSTD_LOGIC; Q :OUTSTD_LOGIC);ENDJKFF1;ARCHITECTUREMAXPLDOFJKFF1ISSIGNALTEMP:STD_LOGIC;BEGINPROCESS(PSET,CLR,CLK)BEGINIF(PSET='0'ANDCLR='1')THENTEMP<='1';ELSIF(PSET='1'ANDCLR='0')THENTEMP<='0';ELSIF(PSET='0'ANDCLR='0')THENNULL;9(CLK'EVENTANDCLK='1')THEN10(J='0'ANDK='0')THENTEMP<=TEMP;ELSIF(J='0'ANDK='1')THENTEMP<='0';ELSIF(J='1'ANDK='0')THENTEMP<='1';ELSIF(J='1'ANDK='1')THENTEMP<=11;ENDIF;ENDIF;ENDPROCESS; Q<=TEMP; END;(五)在下面横线上填上合适的语句，完毕计数器的设计。说明：设电路的控制端均为高电平有效，时钟端CLK,电路的预置数据输入端为4位D，计数输出端也为4位Q，带同步始能EN、异步复位CLR和预置控制LD的六进制减法计数器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT6IS PORT(EN,CLR,LD,CLK:INSTD_LOGIC; D:INSTD_LOGIC_VECTOR(3DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCNT6;ARCHITECTUREBEHAOFCNT6ISSIGNALQTEMP:STD_LOGIC_VECTOR(3DOWNTO0); BEGIN PROCESS(CLK,CLR,LD) BEGIN IFCLR='1'THEN QTEMP<="0000"; --CLR=1清零 ELSIF(CLK'EVENTANDCLK='1')THEN --判断是否上升沿IFLD='1'THEN QTEMP<=12; --判断是否置位 ELSIFEN='1'THEN --判断是否允许计数 IFQTEMP="0000"THENQTEMP<=13; --等于0，计数值置5 ELSEQTEMP<=14; --否则，计数值减1 ENDIF;ENDIF; ENDIF; Q<=QTEMP; ENDPROCESS;ENDBEHA; (六)在下面横线上填上合适的语句，完毕状态机的设计。说明：设计一个双进程状态机，状态0时假如输入”10”则转为下一状态，否则输出”1001”；状态1时假如输入”11”则转为下一状态，否则输出”0101”；状态2时假如输入”01”则转为下一状态，否则输出”1100”；状态3时假如输入”00”则转为状态0，否则输出”0010”。复位时为状态0。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMOORE1ISPORT(DATAIN:INSTD_LOGIC_VECTOR(1DOWNTO0); CLK,RST:INSTD_LOGIC; Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));END;ARCHITECTUREONEOFMOORE1ISTYPEST_TYPEIS(ST0,ST1,ST2,ST3); --定义4个状态SIGNALCST,NST:ST_TYPE; --定义两个信号（现态和次态）SIGNALQ1:STD_LOGIC_VECTOR(3DOWNTO0); BEGINREG:PROCESS(CLK,RST) --主控时序进程BEGINIFRST='1'THEN CST<=15; --异步复位为状态0ELSIFCLK'EVENTANDCLK='1'THEN CST<=16; --现态=次态 ENDIF; ENDPROCESS;COM:PROCESS(CST,DATAIN) BEGIN CASECSTIS WHENST0=>IFDATAIN="10"THENNST<=ST1; ELSENST<=ST0;Q1<="1001";ENDIF; WHENST1=>IFDATAIN="11"THENNST<=ST2; ELSENST<=ST1;Q1<="0101";ENDIF; WHENST2=>IFDATAIN="01"THENNST<=ST3; ELSENST<=ST2;Q1<="1100";ENDIF; WHENST3=>IFDATAIN="00"THENNST<=ST0; ELSENST<=ST3;Q1<="0010";ENDIF; 17;ENDPROCESS;Q<=Q1;END;(七)在下面横线上填上合适的语句，完毕减法器的设计。由两个1位的半减器组成一个1位的全减器--1位半减器的描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYHALF_SUBIS PORT(A,B:INSTD_LOGIC; DIFF,COUT:OUTSTD_LOGIC);ENDHALF_SUB;ARCHITECTUREARTOFHALF_SUBISBEGINCOUT<=18; --借位DIFF<=19; --差END;--1位全减器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYFALF_SUBIS PORT(A,B,CIN:INSTD_LOGIC; DIFF,COUT:OUTSTD_LOGIC);ENDFALF_SUB;ARCHITECTUREARTOFFALF_SUBISCOMPONENTHALF_SUB PORT(A,B:INSTD_LOGIC; DIFF,COUT:OUTSTD_LOGIC);ENDCOMPONENT;20T0,T1,T2:STD_LOGIC;BEGIN U1:HALF_SUBPORTMAP(A,B,21,T1);U2:HALF_SUBPORTMAP(T0,22,23,T2);COUT<=24;END;(八)在下面横线上填上合适的语句，完毕分频器的设计。说明：占空比为1：2的8分频器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCLKDIV8_1TO2IS PORT(CLK:INSTD_LOGIC; CLKOUT:OUTSTD_LOGIC);ENDCLKDIV8_1TO2;ARCHITECTURETWOOFCLKDIV8_1TO2ISSIGNALCNT:STD_LOGIC_VECTOR(1DOWNTO0);SIGNALCK:STD_LOGIC;BEGINPROCESS(CLK)BEGINIFRISING_EDGE(25)THENIFCNT="11"THENCNT<="00";CK<=26;ELSECNT<=27;ENDIF;ENDIF;CLKOUT<=CK;ENDPROCESS;END;(九)在下面横线上填上合适的语句，完毕60进制减计数器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTISPORT(CLK:INSTD_LOGIC;H,L:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOUNT;ARCHITECTUREBHVOFCOUNTISBEGINPROCESS(CLK)VARIABLEHH,LL:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFCLK'EVENTANDCLK='1'THENIFLL=0ANDHH=0THEN HH:="0101"; LL:="1001";ELSIFLL=0THENLL:=28;HH:=29;ELSELL:=30;ENDIF;ENDIF;H<=HH;L<=LL;ENDPROCESS;ENDBHV;（十）在下面横线上填上合适的语句，完毕4-2优先编码器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCODE4IS PORT(A,B,C,D:INSTD_LOGIC; Y0,Y1:OUTSTD_LOGIC);ENDCODE4;ARCHITECTURECODE4OFCODE4ISSIGNALDDD:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALQ:STD_LOGIC_VECTOR(31DOWNTO0);BEGINDDD<=32; PROCESS(DDD) BEGINIF(DDD(0)='0')THENQ<="11"; ELSIF(DDD(1)='0')THENQ<="10";ELSIF(DDD(2)='0')THENQ<="01";ELSEQ<="00";ENDIF;33;Y1<=Q(0); Y0<=Q(1);ENDCODE4;(十一)在下面横线上填上合适的语句，完毕10位二进制加法器电路的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_34.ALL;ENTITYADDER1ISPORT(A,B:INSTD_LOGIC_VECTOR(9DOWNTO0);COUT:OUTSTD_LOGIC;SUM:OUTSTD_LOGIC_VECTOR(9DOWNTO0));END;ARCHITECTUREJGOFADDER1ISSIGNALATEMP:STD_LOGIC_VECTOR(10DOWNTO0);SIGNALBTEMP:STD_LOGIC_VECTOR(10DOWNTO0);SIGNALSUMTEMP:STD_LOGIC_VECTOR(35DOWNTO0);BEGINATEMP<=’0’&A; BTEMP<=’0’&B;SUMTEMP<=36;SUM<=SUMTEMP(9DOWNTO0);COUT<=37;ENDJG;(十二)在下面横线上填上合适的语句，完毕移位寄存器的设计。说明：8位的移位寄存器，具有左移一位或右移一位、并行输入和同步复位的功能。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYSHIFTERISPORT(DATA:INSTD_LOGIC_VECTOR(7DOWNTO0);CLK:INSTD_LOGIC;SHIFTLEFT，SHIFTRIGHT:INSTD_LOGIC;RESET:INSTD_LOGIC;MODE:INSTD_LOGIC_VECTOR(1DOWNTO0);QOUT:BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));ENDSHIFTER;ARCHITECTUREARTOFSHIFTERISBEGINPROCESS BEGIN38(RISING_EDGE(CLK)); --等待上升沿IFRESET='1'THENQOUT<="00000000"; --同步复位ELSECASEMODEISWHEN"01"=>QOUT<=SHIFTRIGHT&39; --右移一位WHEN"10"=>QOUT<=QOUT(6DOWNTO0)&40; --左移一位WHEN"11"=>QOUT<=41; --不移，并行输入WHENOTHERS=>NULL;42;ENDIF;ENDPROCESS;ENDART;(十三)在下面横线上填上合适的语句，完毕计数器的设计。说明：设计一个带有异步复位和时钟使能的一位八进制加法计数器（带进位输出端）。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT8ISPORT(CLK,RST,EN:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(43DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT8;ARCHITECTUREBEHAVOFCNT8ISBEGINPROCESS(CLK,RST,EN) 44CQI:STD_LOGIC_VECTOR(2DOWNTO0); BEGIN IFRST='1'THENCQI:=“000”; 45CLK'EVENTANDCLK='1'THEN IFEN='1'THEN IFCQI<"111"THENCQI:=46; ELSECQI:=47; ENDIF;ENDIF;ENDIF; IFCQI="111"THENCOUT<='1'; ELSECOUT<='0';ENDIF;CQ<=CQI; ENDPROCESS;ENDBEHAV;(十四)在下面横线上填上合适的语句，完毕序列信号发生器的设计。说明：已知发送信号为”10011010”，规定以由高到低的序列形式一位一位的发送，发送开始前及发送完为低电平。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYXULIEISPORT(RES,CLK:INSTD_LOGIC;Y:OUTSTD_LOGIC);END;ARCHITECTUREARCHOFXULIEISSIGNALREG:STD_LOGIC_VECTOR(7DOWNTO0);BEGIN PROCESS(CLK,RES)BEGINIF(CLK’EVENTANDCLK=’1’)THEN IFRES=’1’THEN Y<=’0’; REG<=48; --同步复位，并加载输入ELSEY<=49; --高位输出REG<=50; --左移，低位补0ENDIF;ENDIF;ENDPROCESS;END;(十五)在下面横线上填上合适的语句，完毕数据选择器的设计。说明：采用元件例化的设计方法，先设计一个2选1多路选择器，再使用3个2选1多路选择器构成一个4选1多路选择器。LIBRARYIEEE; --2选1多路选择器的描述USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX21IS PORT(A,B,SEL:INSTD_LOGIC; Y:OUTSTD_LOGIC);ENDMUX21;ARCHITECTUREARTOFMUX21ISBEGINY<=AWHENSEL='0' ELSE B; END;LIBRARYIEEE; --4选1多路选择器的描述USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41IS PORT(A,B,C,D:INSTD_LOGIC; S1,S2:INSTD_LOGIC; Y:OUTSTD_LOGIC);END;ARCHITECTUREARTOFMUX41ISCOMPONENTMUX41 PORT(A,B,SEL:INSTD_LOGIC; Y:OUTSTD_LOGIC);ENDCOMPONENT;51Y1,Y2:STD_LOGIC;BEGINU1:MUX21PORTMAP(A,B,S1,52);U2:MUX21PORTMAP(C,D,52,Y2);U2:MUX21PORTMAP(Y1,Y2,54,Y);END;(十六)在下面横线上填上合适的语句，完毕8位奇偶校验电路的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYPCIS PORT( A :INSTD_LOGIC_VECTOR(7DOWNTO0); Y :OUTSTD_LOGIC );ENDPC;ARCHITECTUREAOFPCIS BEGIN PROCESS(A). VARIABLETMP:STD_LOGIC; BEGIN TMP55'0'; FORIIN0TO7LOOPTMP:=56; ENDLOOP; Y<=57; ENDPROCESS; END;（十七）在下面横线上填上合适的语句，完毕一个逻辑电路的设计，其布尔方程为Y=(A+B)(C⊙D)+(B⊕F).LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYCOMBIS PORT(A,B,C,D,E,F,:INSTD_LOGIC; Y:OUTSTD_LOGIC);ENDCOMB;ARCHITECTUREONEOFCOMBISBEGINY<=(AORB)AND(C58D)OR(B59F);ENDARCHITECTUREONE;（十八）在下面横线上填上合适的语句，完毕一个带使能功能的二-十进制译码器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMY2TO10ISPORT(EN:INSTD_LOGIC; DIN:INSTD_LOGIC_VECTOR(60DOWNTO0);POUT:OUTSTD_LOGIC_VECTOR(9DOWNTO0));END;ARCHITECTUREARCHOFMY2TO10ISBEGINPROCESS(EN,DIN)BEGINIFEN=’1’THENCASEDINISWHEN"0000"=>POUT<="";WHEN"0001"=>POUT<="";WHEN"0010"=>POUT<="";WHEN"0011"=>POUT<="";WHEN"0100"=>POUT<="";WHEN"0101"=>POUT<="";WHEN"0110"=>POUT<="";WHEN"0111"=>POUT<="";WHEN"1000"=>POUT<="";WHEN"1001"=>POUT<="";WHENOTHERS=>POUT<="";ENDCASE;ENDIF;ENDPROCESS;END;（十九）在下面横线上填上合适的语句，完毕下降沿触发的D触发器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFFISPORT(D,CLK:INSTD_LOGIC;Q,QB:OUTSTD_LOGIC);ENDDFF;ARCHITECTUREBEHAVEOFDFFISBEGINPROCESS(CLK)BEGINIF61ANDCLK'EVENTTHENQ<=62;QB<=NOTD;ENDIF;ENDPROCESS;ENDBEHAVE;（二十）在下面横线上填上合适的语句，完毕移位寄存器的设计。说明：4位串入-串出移位寄存器有有1个串行数据输入端（DI）、1个串行数据输出输出端（DO）和1个时钟输入端（CLK）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSISOISPORT(DI:INSTD_LOGIC;CLK:INSTD_LOGIC;DO:OUTSTD_LOGIC);ENDSISO;ARCHITECTUREAOFSISOISSIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,DI)BEGINIFCLK’EVENTANDCLK=’1’THENQ(0)<=63;FOR64LOOPQ(I)<=65;ENDIF;ENDPROCESS;DO<=Q(3);ENDA;（二十一）在下面横线上填上合适的语句，完毕同步22进制计数器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTER22ISPORT(CLK:INSTD_LOGIC; CH,C:OUTSTD_LOGIC; QB1,QA1:OUTSTD_LOGIC_VECTOR(3DOWNTO0));END;ARCHITECTUREBEHAVOFCOUNTER22ISSIGNALQB,QA:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALCIN:STD_LOGIC;BEGINQB1<=QB;QA1<=QA;PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENIF(QA=66)OR(QB=2ANDQA=1)THENQA<="0000";CIN<='0';ELSIFQA=67THENCIN<='1';QA<=QA+1;ELSEQA<=68;CIN<='0';ENDIF;ENDIF;ENDPROCESS;PROCESS(CIN,CLK)BEGINIFCLK'EVENTANDCLK='1'THENIF(QB=2ANDQA=1)THENQB<=69;C<='1';ELSEC<=70;ENDIF;IFCIN='1'THENQB<=71;ENDIF;ENDIF;ENDPROCESS;CH<=CIN;END;（二十二）在下面横线上填上合适的语句，完毕一个“01111110”序列发生器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYSENQGENISPORT(CLK,CLR,CLOCK:INSTD_LOGIC;ZO:OUTSTD_LOGIC);END;ARCHITECTUREARTOFSENQGENISSIGNALCOUNT:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALZ:STD_LOGIC:='0';BEGINPROCESS(CLK,CLR)BEGINIFCLR='1'THENCOUNT<="000";ELSEIFCLK='1'ANDCLK'EVENTTHENIFCOUNT=72THENCOUNT<="000";ELSECOUNT<=COUNT+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(COUNT)BEGINCASECOUNTISWHEN"000"=>Z<='0';WHEN"001"=>Z<='1';WHEN"010"=>Z<='1';WHEN"011"=>Z<='1';WHEN"100"=>Z<='1';WHEN"101"=>Z<='1';WHEN"110"=>Z<='1';WHENOTHERS=>Z<=73;ENDCASE;ENDPROCESS;PROCESS(CLOCK,Z)BEGINIFCLOCK='1'ANDCLOCK'EVENTTHENZO<=74;ENDIF;ENDPROCESS;ENDART;（二十三）在下面横线上填上合适的语句，完毕一个“01111110”序列信号检测器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDETECTISPORT(DATAIN:INSTD_LOGIC;CLK:INSTD_LOGIC;Q:BUFFERSTD_LOGIC);ENDDETECT;ARCHITECTUREARTOFDETECTISTYPESTATETYPEIS(S0,S1,S2,S3,S4,S5,S6,S7,S8);BEGINPROCESS(CLK)VARIABLE75:76;BEGINQ<='0';CASEPRESENT_STATEISWHENS0=>IFDATAIN='0'THENPRESENT_STATE:=S1;ELSEPRESENT_STATE:=S0;ENDIF;WHENS1=>IFDATAIN='1'THENPRESENT_STATE:=S2;ELSEPRESENT_STATE:=S1;ENDIF;WHENS2=>IFDATAIN='1'THENPRESENT_STATE:=S3;ELSEPRESENT_STATE:=S1;ENDIF;WHENS3=>IFDATAIN='1'THENPRESENT_STATE:=S4;ELSEPRESENT_STATE:=S1;ENDIF;WHENS4=>IFDATAIN='1'THENPRESENT_STATE:=S5;ELSEPRESENT_STATE:=S1;ENDIF;WHENS5=>IFDATAIN='1'THENPRESENT_STATE:=S6;ELSEPRESENT_STATE:=S1;ENDIF;WHENS6=>IFDATAIN='1'THENPRESENT_STATE:=S7;ELSEPRESENT_STATE:=S1;ENDIF;WHENS7=>IFDATAIN='0'THENPRESENT_STATE:=S8;Q<='1';ELSEPRESENT_STATE:=S0;ENDIF;WHENS8=>IFDATAIN='0'THENPRESENT_STATE:=77;ELSEPRESENT_STATE:=78;ENDIF;ENDCASE;79CLK='1';ENDPROCESS;ENDART;（二十四）在下面横线上填上合适的语句，完毕序列信号发生器的设计。说明：带异步复位为CLR，时钟端为CLK，输出端为Q，串行输出指定序列（低位先出）。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSENQGENIS PORT(CLR,CLK:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDSENQGEN;ARCHITECTUREBEHAOFSENQGENISSIGNALQ_TEMP:STD_LOGIC_VECTOR(2DOWNTO0); BEGIN PROCESS(CLK,CLR) BEGIN IFCLR='1'THEN Q_TEMP<="000"; 80(CLK'EVENTANDCLK='1')THEN IFQ_TEMP="111"THEN Q_TEMP<="000"; 81Q_TEMP<=Q_TEMP+1; ENDIF; 82; ENDPROCESS;PROCESS(Q_TEMP)BEGINCASEQ_TEMPISWHEN"000"=>Q<='0';WHEN"001"=>Q<='1';WHEN"010"=>Q<='0';WHEN"011"=>Q<='1';WHEN"100"=>Q<='1';WHEN"101"=>Q<='1';WHEN"110"=>Q<='1';WHEN"111"=>Q<='0';WHENOTHERS=>83;ENDCASE;ENDPROCESS;ENDBEHA;（二十五）在下面横线上填上合适的语句，完毕七人表决器的设计。说明：一个带输出显示的七人表决器(两种结果：批准，反对)。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYBIAOJUE7IS PORT(D:INSTD_LOGIC_VECTOR(0TO6); RLED,GLED:OUTSTD_LOGIC;LEDSEG:OUTSTD_LOGIC_VECTOR(6DOWNTO0));END;ARCHITECTUREBEVOFBIAOJUE7ISBEGINPROCESS(D)VARIABLECOUNT:INTEGERRANGE0TO7;BEGINCOUNT:=84;FOR85LOOPIFD(I)='1'THENCOUNT:=86;ELSECOUNT:=COUNT;ENDIF;ENDLOOP;IFCOUNT>87THEN GLED<='1'; RLED<='0';ELSE GLED<='0'; RLED<='1';ENDIF;CASECOUNTISWHEN0=>LEDSEG<="0111111";WHEN1=>LEDSEG<="0000110";WHEN2=>LEDSEG<="1011011";WHEN3=>LEDSEG<="1001111";WHEN4=>LEDSEG<="1100110";WHEN5=>LEDSEG<="1101101";WHEN6=>LEDSEG<="1111101";WHEN7=>LEDSEG<="0100111";ENDCASE;ENDPROCESS;ENDBEV;（二十六）在下面横线上填上合适的语句，完毕有限状态机的设计。说明：状态转换图如右图，S0~S3为状态号，圈内为输出。LIBRARY1EEE；USEIEEE．STD_LOGIC_1164．ALL；ENTITYS_MACHINEISPORT(CLK,RESET：INSTD_LOGIC;INPUTS：INSTD_LOGIC_VECTOR(0TO1)；OUTPUTS：OUTINTEGERRANGE(0TO15)；ENDS_MACHINE；ARCHITECTUREBEHAVOFS_MACHINEISTYPESTATESIS(S0，S1,S2，S3)；SIGNALCURCENT_STATE，NEXT_STATE：STATES；BEGINREG:PROCESS(RESET，CLK)--状态切换BEGINIFRESET=‘1’THENCURRENT_STATE<=S0；ELSIFCLK=’L’ANDCLK‘EVENTTHENCURRENT_STATE<=NEXT_STATE；ENDIF;ENDPROCESS；COM:PROCESS(CURRENT_STATE，INPUTS)--下一状态、BEGINCASECURRENT_STATEISWHENS0=>OUTPUTS<=88；IFINPUTS=”00”THENNEXT_STATE<=S0;ELSENEXT_STATE<=SL；ENDIF；WHENSL=>OUTPUTS<=8；IFINPUTS=89THENNEXT_STATE<=90;ELSENEXT_STATE<=S2；ENDIF；WHENS2=>OUTPUTS<=12;IFINPUTS=“11”THENNEXT_STATE<=S0;ELSENEXT_STATE<=S3;ENDIF;WHENS3=>OUTPUTS<=14;IFINPUTS=“11”THENNEXT_STATE<=S3;；ELSENEXTSTATE<=S0;ENDIF；ENDCASE;91;ENDBEHAV;（二十七）在下面横线上填上合适的语句，完毕移位寄存器74166的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYTTL74166ISPORT(A,B,C,D,E,F,G,H:INSTD_LOGIC; --8位并行输入信号CLK:INSTD_LOGIC; --时钟信号RESET:INSTD_LOGIC; --复位信号SE:INSTD_LOGIC; --串行输入信号FE:INSTD_LOGIC; --时钟信号严禁端SL:INSTD_LOGIC; --移位装载控制端Q:OUTSTD_LOGIC); --串行输出信号ENDTTL74166;ARCHITECTUREARTOFTTL74166ISSIGNALTMPREG8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,RESET,SL,FE)BEGINIFRESET='1'THENTMPREG8<=92;Q<=TMPREG8(7);ELSIFCLK'EVENTANDCLK='1'THENIFFE='0'THENIFSL='0'THENTMPREG8(0)<=A;TMPREG8(1)<=B;TMPREG8(2)<=C;TMPREG8(3)<=D;TMPREG8(4)<=E;TMPREG8(5)<=F;TMPREG8(6)<=G;TMPREG8(7)<=H;93SL='1'THENFORIINTMPREG8'HIGHDOWNTO94LOOPTMPREG8(I)<=95;ENDLOOP;TMPREG8(TMPREG8'LOW)<=96;Q<=97;ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDART;（二十八）在下面横线上填上合适的语句，完毕8位双向总线缓冲器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYTRI_BIGATEISPORT(A,B:INOUTSTD_LOGIC_VECTOR(7DOWNTO0); EN,DR:INSTD_LOGIC);END;ARCHITECTURERTLOFTRI_BIGATEISSIGNALAOUT,BOUT:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(A,DR,EN)BEGIN IF(EN=‘0’)AND(DR=‘1’)THENBOUT<=A;ELSE BOUT<=“ZZZZZZZZ”;ENDIF; B<=BOUT;ENDPROCESS;PROCESS(B,DR,EN)BEGINIF(EN=‘0’)AND(DR=‘0’)THEN AOUT<=98;ELSE AOUT<=99;ENDIF;A<=100;ENDPROCESS;END;（二十九）在下面横线上填上合适的语句，完毕4位串入/并出移位寄存器的设计。说明：4位串入/并出移位寄存器可以用D触发器组成。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFFISPORT(D,CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDDFF;ARCHITECTUREBEHAVEOFDFFISBEGINPROCESS(CLK)BEGINIFCLK='0'ANDCLK'EVENTTHENQ<=D;ENDIF;ENDPROCESS;ENDBEHAVE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSHIFTIS PORT(A,CLK:INSTD_LOGIC; D:OUTSTD_LOGIC);ENDSHIFT;ARCHITECTURESHIFT1OFSHIFTISCOMPONENTDFF1 PORT(D,CLK:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALZ:STD_LOGIC_VECTOR(0TO4);BEGINZ(0)<=101; G1:FOR102GENERATE DFFX:DFF1PORTMAP(Z(I),CLK,103); ENDGENERATE; D<=104;ENDSHIFT1;（三十）在下面横线上填上合适的语句，完毕4位异步计数器的设计。说明：4位异步计数器可以用D触发器器组成。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1ISPORT(D,CLK:INSTD_LOGIC;Q,QB:OUTSTD_LOGIC);ENDDFF1;ARCHITECTUREBEHAVEOFDFF1ISBEGINPROCESS(CLK)BEGINIFCLK='1'ANDCLK'EVENTTHENQ<=D;QB<=NOTD;ENDIF;ENDPROCESS;ENDBEHAVE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYRPLCONTIS PORT(CLK:INSTD_LOGIC; COUNT:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDRPLCONT;ARCHITECTURERPLCONTOFRPLCONTISCOMPONENTDFF1 PORT(CLK,D:INSTD_LOGIC;Q,QB:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALCOUNT_IN_BAR:STD_LOGIC_VECTOR(4DOWNTO0);BEGINCOUNT_IN_BAR(0)<=CLK;GEN1:FORIIN0TO3GENERATE U:DFF1PORTMAP(CLK=>105, D=>106, Q=>107,QB=>108);ENDGENERATE;ENDRPLCONT;（三十一）在下面横线上填上合适的语句，完毕交通灯控制器的设计。说明：红、黄、绿灯分别亮10秒，状态0时东西绿灯亮，南北红灯亮；状态1时东西绿、黄灯亮，南北红灯亮；状态2时东西红灯亮，南北绿灯亮；状态3时东西红灯亮，南北绿、黄灯亮。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYTRAFFICLED1ISPORT(CLK,RESET:INSTD_LOGIC; Q:OUTSTD_LOGIC_VECTOR(11DOWNTO0));END;ARCHITECTUREONEOFTRAFFICLED1ISSIGNALY_EWSN,G_EWSN,R_EWSN:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALCOUNT:INTEGERRANGE0TO9;SIGNALSTATE:INTEGERRANGE0TO3;BEGINPROCESS(RESET,CLK,COUNT)BEGINIFRESET='1'THENCOUNT<=0; STATE<=0;ELSIFCLK'EVENTANDCLK='1'THEN COUNT<=COUNT+1; IF(COUNT=109)THENSTATE<=STATE+1;ENDIF; IFSTATE>110THENSTATE<=0; ENDIF;ENDIF;CASESTATEISWHEN0=>Y_EWSN<="0000";G_EWSN<="1100"; R_EWSN<="0011";WHEN1=>Y_EWSN<="1100";G_EWSN<="1100"; R_EWSN<="0011";WHEN2=>Y_EWSN<="0000";G_EWSN<="0011"; R_EWSN<="1100";WHEN3=>Y_EWSN<="0011";G_EWSN<="0011"; R_EWSN<="1100";WHENOTHERS=>111;ENDCASE;ENDPROCESS;Q(0)<=R_EWSN(0);Q(1)<=G_EWSN(0);Q(2)<=Y_EWSN(0);Q(3)<=R_EWSN(2);Q(4)<=G_EWSN(2);Q(5)<=Y_EWSN(2);Q(6)<=R_EWSN(1);Q(7)<=G_EWSN(1);Q(8)<=Y_EWSN(1);Q(9)<=R_EWSN(3);Q(10)<=G_EWSN(3);Q(11)<=Y_EWSN(3);END;（三十二）在下面横线上填上合适的语句，完毕8位数字比较器的设计。ENTITYCOMPISPORT(A,B:IN112RANGE0T0113;AEQUALB,AGREATB,ALESSB:OUTBIT);ENDCOMP;ARCHITECTUREBEHAVEOFCOMPISBEGINAEQUALB＜＝‘1’WHENA＝BELSE‘0’;AGREATB＜＝‘1’WHENA＞BELSE‘0’;ALESSB＜＝‘1’WHENA＜BELSE‘0’;ENDBEHAVE;（三十三）在下面横线上填上合适的语句，完毕一个16个字节的堆栈的设计。说明：堆栈有复位信号、压栈/弹栈信号、堆栈满信号、数据输入/输出口。LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；USEIEEE.STD_LOGIC_SIGNED.ALL；ENTITYSTACKISPORT(DATAIN :INSTD_LOGIC_VECTOR(7DOWNTO0);PUSH,POP,RESET,CLK :INSTD_LOGIC;STACKFULL:OUTSTD_LOGIC;DATAOUT:BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));ENDSTACK;ARCHITECTUREAOFSTACKISTYPEARRAYLOGICISARRAY(15DOWTO0)OFSTD_LOGIC_VECTOR(7DOWNTO0); --定义一个16字节数据类型SIGNALDATA:ARRAYLOGIC； --此处定义了DATA为一个数组16×8SIGNALSTACKFLAG:STD_LOGIC_VECTOR(15DOWNTO0); --定义堆栈标志，每一字节有数据为1，无数据为0BEGINSTACKFULL＜＝114; --字节0为栈底PROCESS(CLK,NRESET,POP,PUSH)BEGINIFRESET=‘1’THENSTACKFLAG＜＝(OTHERS=>‘0’);DATAOUT＜＝(OTHERS=>‘0’);FORIIN0TO15LOOPDATA(I)＜＝115;ENDLOOP;ELSIFCLK’EVENTANDCLK=‘1’THENIFPUSH=‘1’ANDPOP=‘0’THEN --PUSHFORIIN0TO14LOOPDATA(I)＜＝116;ENDLOOP;DATA(15)＜＝117;STACKFLAG＜＝‘1’&STACKFLAG(15DOWNTO1);ELSIFPUSH=‘0’ANDPOP=‘1’THEN --POPDATAOUT＜＝DATA(15);FORIIN15DOWNTO1LOOPDATA(I)＜＝118;ENDLOOP；STACKFLAG＜＝STACKFLAG(119DOWNTO0)&‘0’;ENDIF；ENDIF；ENDPROCESS;ENDA;（三十四）在下面横线上填上合适的语句，完毕一个8位分频器的设计。LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPULSEISPORT(CLK :INSTD_LOGIC;D :INSTD_LOGIC_VECTOR(7DOWNTO0);FOUT :OUTSTD_LOGIC);END;ARCHITECTUREONEOFPULSEISSIGNALFULL:STD_LOGIC;BEGIN P_REG:PROCESS(CLK) 120CNT8:STD_LOGIC_VECTOR(7DOWNTO0); BEGIN IFCLK’EVENTANDCLK=‘1’THEN IFCNT8="11111111"THEN CNT8:=121;--当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL<='1';--同时使溢出标志信号FULL输出为高电平 ELSECNT8:=122;--否则继续作加1计数 FULL<='0';--且输出溢出标志信号FULL为低电平 ENDIF; ENDIF; ENDPROCESSP_REG; P_DIV:PROCESS(123) VARIABLECNT2:STD_LOGIC; BEGIN IFFULL'EVENTANDFULL='1'THEN CNT2<=124;--假如溢出标志信号FULL为高电平，D触发器输出取反 IFCNT2='1'THENFOUT<='1'; ELSE FOUT<='0'; ENDIF; ENDIF;ENDPROCESSP_DIV;END;（三十五）在下面横线上填上合适的语句，完毕一个10线－4线优先编码器的设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCODERISPORT(DIN:INSTD_LOGIC_VECTOR(9DOWNTO0);OUTPUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCODER;ARCHITECTUREBEHAVOFCODERISSIGNALSIN:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(125)BEGINIF(DIN(9)='0')THENSIN<="1001";126(DIN(8)=’0’)THENSIN<="1000";ELSIF(DIN(7)='0')THENSIN<="0111";ELSIF(DIN(6)='0')THENSIN<="0110";ELSIF(DIN(5)='0')THENSIN<="0101";ELSIF(DIN(4)='0')THENSIN<="0100";ELSIF(DIN(3)='0')THENSIN<="0011";ELSIF(DIN(2)='0')THENSIN<="0010";ELSIF(DIN(1)='0')THENSIN<="0001";ELSESIN<=127;128；ENDPROCESS；OUTPUT<=SIN；ENDBEHAV;（三十六）在下面横线上填上合适的语句，完毕一个摩尔状态机的设计。说明:状态机的状态图见图A,状态结构图见图B.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMOOREBIS PORT(CLK,RESET:INSTD_LOGIC; INA:INSTD_LOGIC_VECTOR(1DOWNTO0); OUTA:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDMOOREB;ARCHITECTUREONEOFMOOREBIS TYPEMS_STATEIS(ST0,ST1,ST2,ST3); SIGNALC_ST,N_ST:129;BEGIN PROCESS(CLK,RESET) BEGIN IFRESET=‘1’THENC_ST<=ST0; ELSIFCLK’EVENTANDCLK=‘1’THENC_ST<=130; ENDIF; ENDPROCESS; PROCESS(C_ST) BEGIN CASEC_STIS WHENST0=>IFINA=“00”THENN_ST<=ST0; ELSEN_ST<=ST1; ENDIF; OUTA<=“0101”; WHENST1=>IFINA=“00”THENN_ST<=ST1; ELSEN_ST<=ST2; ENDIF; OUTA<=“1000”; WHENST2=>IFINA=“11”THENN_ST<=131; ELSEN_ST<=ST3; ENDIF; OUTA<=“1100”; WHENST3=>IFINA=“11”THENN_ST<=132; ELSEN_ST<=ST0; ENDIF; OUTA<=133; WHENOTHERS=>N_ST<=ST0; ENDCASE; ENDPROCESS;ENDONE;（三十七）在下面横线上填上