第1章-绪论英文姜老师

计算机组成原理软件学院毛克明了解并掌握计算机硬件的基本知识；在此基础上着重讲述计算机中“数”的运算存储计算机(CPU)的设计和工作原理以及输入输出系统。课程目的和安排主要教学目标：在软件（包括系统软件和应用软件）设计过程中必须要了解到的计算机系统的组成与结构。通过本课程学习，能够比较全面地掌握计算机系统的基本概念、基本原理、基本结构和基本分析方法，并建立起计算机系统的完整概念。学会计算机系统各个主要组成部分的基本原理，常用的性能评价方法，分析方法、计算方法等。课程目的和安排内容安排:课堂授课32学时实验8学时绪论（2学时）计算机中的信息表示（4学时）组合线路的逻辑设计（2学时）时序线路的逻辑设计（2学时）算术逻辑单元（2学时）复杂算术操作（4学时）指令系统结构（2学时）中央处理器（2学时）控制器（4学时）存储器（6学时）输入输出（2学时）考核方式及成绩评定总分100分三部分组成平时成绩：20%（出勤率，作业）实验成绩：10%（共两次实验）期末试卷成绩：70%期末考试方式：闭卷教材及参考书教材：LanJin,BoHatfield.ComputerOrganizationPrinciples,Analysis,andDesign清华大学出版社参考书：《计算机组成原理》白中英第四版《计算机组成与结构》王爱英清华大学《计算机系统结构：一种定量的方法》JohnL.Hennessy,David,A.Patterson著ComputerOrganizationChapter1IntroductionChapter1Introduction1.1TheScopeofComputerArchitectureandOrganization1.2ModelingComputerOrganization1.3AHistoricalSketchofComputerEvolution1.4RepresentativeComputerFamilies1.5PerspectivesoftheComputerEvolution1.6Summary1.1TheScopeofComputerA&OMulti-layeredstructureofacomputersystemApplicationSoftwareUserinterfacesSystemSoftwareSysteminterfacesOSDataabstract：servicesusersthroughsystemlibraries;Resourceabstract：supervisehardwarethroughsystemcall;SoftwareHardwareHardwareSystemC,M,C,I,O,CommI/O

Comm.Inter.HardwareDeviceInstructionsetarchitecture;Computerorganization;ImplementationFig1.1Multi-layeredstructureofacomputersystemI,O,Comm.Exceptionhandlingmechanism1.1TheScopeofComputerA&OHardwaresystemLayerInstructionsetarchitectureInstructionsetdesignComputerorganizationfunctionunitsandtheirinterrelationshipControlunitforinstructionsetimplementationinstructionsetimplementationlogicallyImplementationDesignlogicalcircuitandfunctionbyIntegratedcircuitandotherhardwarePhysicallyimplementation1.2ModelingComputerOrganizationThelayeredstructureofcomputerdesignprocessInstructionSetArchitectureLevelInstructionsetdesignLogicalSystemDesignLevelDatapathDesignControlSequenceDesignLevelControlunitdesignDigitalLogicalDesignLevelImplementationofsystemdesignFig1.2Themulti-layeredstructureofthecomputerdesignprocess1.2ModelingComputerOrganizationTheRTLModelofComputerOrganization （Register-TransferLevel）Graphicalform：usediagramstodescribethelogicstructuresofthedatapathTextualform：useaRTLlanguagetodescribethecontrolprocess1.2ModelingComputerOrganizationRTLmodelofacentralprocessingunitControlSectionIRPCMARMBRALUMemorybusGPRTempCPUregistersControlregistersMemoryregistersexample1.2ModelingComputerOrganizationIR:InstructorRegister指令寄存器ALU:ArithmeticLogicUnit算术逻辑单元GPR:General-PurposeRegister通用寄存器Temp:存储器PC:ProgramCounter程序计数器MAR:MemoryAddressRegister记忆体地址寄存器MBR:MemoryBufferRegister记忆体缓冲暂存器1.2ModelingComputerOrganizationControlsequenceofinstructionfetchSendtheaddressoftheinstructiontobefetchedfromtheprogramcounter(PC)tothememoryaddressregister(MAR)Asserta“readmemory”commandtothememorymoduleandwaituntiltheinstructionisavailableinthememorybufferregister（MBR）ThecontentofthePCisincrementedby1sothatitwillpointtotheaddressofthenextinstructionLoadthenewinstructionfromthememorybufferregister（MBR）totheinstructionregister（IR）Deasertthe“readmemory”commandexample1.2ModelingComputerOrganizationInstructionfetch,writteninRTLlanguage:MARPC；memory_read1PCPC

+1Waituntilready=1IRMBRmemory_read0example1.2ModelingComputerOrganizationWeassumethecontrolcyclesforaninstructionfetcharesynchronizedwiththecentralclock,sothewaitcommandintheabovesequenceisomittedMAR（PC）；ReadM

；impliesReadM1

；effectiveonlyinonecycle,soReadM0isunnecessaryPC（PC）+1IRMBRexample1.2ModelingComputerOrganizationTheperformancemodelofacomputersystemMultilayeredstructure.Evaluatetheperformanceofthesystemiscomplex.performanceofhardwarefixedparameterseasytotestperformanceofprogramtestforstandardprogramhowtochoosetestedprogram1.2ModelingComputerOrganizationTheperformancemodelofacomputersystemtwoperformancemeasuresMIPSorMFLOPS（每秒百万条指令或每秒百万次浮点操作）T（CPUexecutiontime）：quantifytheeffectivespeedofthecombinedhardware/softwaresystem. MIPS=f(MHz)/CPIave T(sec)=IC×CPIave/f(Hz)AssumethatweknowtheaveragenumberofcyclesperinstructionCPIavewherefistheclockfrequencyandICistheinstructioncount,i.e.,thetotalnumberofinstructionsintherunningprogram1.2ModelingComputerOrganizationCalculationoftheoriginalperformanceofacomputerSupposeacomputerwithaclockfrequencyof100MHzasfourtypesofinstructions,andthefrequencyofusageandtheCPIforeachofthemaregivenintable.FindtheMIPSofthecomputerandtheCPUtimerequiredtorunaprogramof107instructions.ex1.11.2ModelingComputerOrganizationFindtheaverageCPIave:CPIave=0.4*2+0.3*4+0.08*2.5+0.22*3 =0.8+1.2+0.2+0.66=2.86MIPS=100/2.86=35T=107*2.86/(100*106)

=0.286s

MIPS=f(MHz)/CPIaveT(sec)=IC×CPIave/f(Hz)ex1.11.2ModelingComputerOrganizationCalculationoftheupdatedperformanceofacomputerCombiningcomparingandbranchinstructionstogethersothatcompareinstructionscanbereplacedandremoved.Supposeeachcompareinstructionwasoriginallyusedwithonebranchinstruction,andnoweachbranchinstructionischangedtoacompare&branchinstruction.Alsosupposethatthenewproposalwoulddecreasetheclockfrequencyby5%,becausethenowcompare&branchinstructionneedsmoretimetoexecute.FindthenewCPIave,MIPS,andT.CPIave=(0.4*2+0.3*4+0.08*2.5+0.22*3)/0.92 =2.66/0.92=2.9MIPS=(100*95%)/2.9=32.76T=(0.92*107)

*2.9/(0.95*100*106)

=0.28sex1.21.2ModelingComputerOrganizationComparingtheresultsofEX1.1andEx1.2,weseethatthenewproposallowerstheMIPSrate,butdecreasestheexecutiontimeoftheprogram.Thenewproposalisasoftwaremeansthatimprovesthesoftwarecode,butworsensthehardware.Onlytheprogramexecutiontimereflectsthetrueperformanceofthecomputer.Theperformancemodelcanbeappliedtosuperscalar（超标量）andpipelined（流水线）processorsaswell.Speedup（加速比）canbeusedtodescribetheirperformances.Sk=kd （kinstructionpipelines,eachwithdepthd）1.3AHistoricalSketchofComputerEvolutionThefirstGeneration:1946-1957，VacuumTubes（真空管）ThesecondGeneration:1958-1964，Transistors

（晶体管）ThethirdGeneration:1965-1971Smallscaleintegration，Upto100devicesonachipMediumscaleintegration，100-3,000devicesonachipThefourthGeneration:1972-1977Largescaleintegration（LSI），3,000-100,000devicesonachipThefifthGeneration:1978todateVerylargescaleintegration（VLSI），100,000-100,000,000devicesonachipUltralargescaleintegration，Over100,000,000devicesonachip1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC(EckertandMauchly埃克特24,莫奇利36

)EDVAC(vonNeumann)IAS (PrincetonInstituteforAdvancedStudies

)UNIVAC(CommercialComputers)1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC(EckertandMauchly埃克特24,莫奇利36

)VacuumTubesENIAC-photo1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC：

backgroundElectronicNumericalIntegratorAndComputer（电子数字积分器和计算器）EckertandMauchly(埃克特24,莫奇利36)UniversityofPennsylvania（宾夕法尼亚大学）Trajectorytablesforweapons

(计算新武器的射程及弹道表）Started1943,Finished1946ToolateforwareffortUseduntil19551.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC：

detailsDecimal(notbinary)20accumulators(累加器)of10digitsProgrammedmanuallybyswitches&cables18,000vacuumtubes30tons15,000squarefeet140kWpowerconsumption5,000additionspersecond1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationEDVACElectronicDiscreteVariableComputer（电子离散变量计算机）1945vonNeumannTuring1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationvonNeumann/Turing

StoredProgramconcept(1945)Programcouldberepresentedinaformsuitableforstoringinmemory,andaprogramcouldbesetoralteredbysettingthevaluesofaportionofmemory1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationStructureofvonNuemannmachineMainMemoryArithmeticandLogicUnitProgramControlUnitInputOutputEquipment1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIASComputer

：

(1946)PrincetonInstituteforAdvancedStudies（普林斯顿高级研究院）Completed1952Prototypeofallsubsequentgeneral-purposecomputers（后来通用计算机的原型）1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIAS：details1000x40bitwords(memory)(1000个存储单元)Binarynumber（数据和指令都以2进制存储）2x20bitinstructions（一个字包含2个指令）NumberWord1+39InstructionWordOpcode8Address12Opcode操作码Address符号数值1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIAS：detailsSetofregisters(storageinCPU)MemoryBufferRegister(MBR)

存储缓冲寄存器MemoryAddressRegister(MAR)

存储地址寄存器InstructionRegister(IR)

指令寄存器InstructionBufferRegister(IBR)

指令缓冲寄存器ProgramCounter(PC)

程序计数器Accumulator(AC)

累加器MultiplierQuotient(MQ)

乘商寄存器StructureofIAS–

detailALUACControlunitdecoderIRPCARCLAInstructionflow1CPUcycle1234DR562CPUcycle789ALUACControlunitdecoderIRPCARDRADDInstructionflow2CPUCycle1234453CPUcycleALUACcontroldecoderIRPCARDRSTAinstructionflow2CPUcycle231453CPUcycleALUACcontroldecoderIRPCARDRNOP指令流程第1个CPU周期第2个CPU周期JMPInstructionflow1CPUcycle2CPUcycle1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationTuringMachine1.3AHistoricalSketchofComputerEvolutionCommercialComputers

：

Eckert-Mauchly

1947-ComputerCorporationUNIVACI(UniversalAutomaticComputer)（通用自动化计算机）USBureauofCensus1950calculations（美国统计局委托制造用于1950年的计算）BecamepartofSperry-RandCorporationLate1950s-UNIVACIIFasterMorememory1.3AHistoricalSketchofComputerEvolutionCommercialComputers

：IBMPunched-cardprocessingequipment1953-the701IBM’sfirststoredprogramcomputerScientificcalculations1955-the702BusinessapplicationsLeadto700/7000series1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationTransistors（晶体管）1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationReplacedvacuumtubesSmallerCheaperLessheatdissipationSolidStatedevice（固态器件）MadefromSilicon(Sand)（由硅片制成）Invented1947atBellLabsWilliamShockleyetal.1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationSecondgenerationmachinesNCR&RCAproducedsmalltransistormachinesIBM7000DEC-1957ProducedPDP-11.3AHistoricalSketchofComputerEvolutionTheSecondGenerationSecondgenerationmachines1.3AHistoricalSketchofComputerEvolutionTheThirdGeneration

Microelectronics

（微电子学）Literally-“smallelectronics”Acomputerismadeupofgates,memorycellsandinterconnectionsThesecanbemanufacturedonasemiconductor（半导体）e.g.siliconwafer（硅晶片）1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）IncreaseddensityofcomponentsonchipGordonMoore-cofounderofIntelNumberoftransistorsonachipwilldoubleeveryyear（芯片上的晶体管数量每年翻一翻）1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）

GrowthinCPUTransistorCount

1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）Since1970’sdevelopmenthasslowedalittleNumberoftransistorsdoublesevery18monthsCostofachiphasremainedalmostunchangedHigherpackingdensitymeansshorterelectricalpaths,givinghigherperformanceSmallersizegivesincreasedflexibilityReducedpowerandcoolingrequirementsFewerinterconnectionsincreasesreliability1.3AHistoricalSketchofComputerEvolutionIBM360series1964Replaced(¬compatiblewith)7000seriesFirstplanned“family”ofcomputersSimilaroridenticalinstructionsetsSimilaroridenticalO/SIncreasingspeedIncreasingnumberofI/Oports(i.e.moreterminals)IncreasedmemorysizeIncreasedcostMultiplexedswitchstructure1.3AHistoricalSketchofComputerEvolutionDECPDP-8

1964Firstminicomputer(afterminiskirt!)DidnotneedairconditionedroomSmallenoughtositonalabbenchEmbeddedapplications&OEMBUSSTRUCTURE1.3AHistoricalSketchofComputerEvolutionDECPDP-8

：BusStructureOMNIBUSConsoleControllerCPUMainMemoryI/OModuleI/OModule1.3AHistoricalSketchofComputerEvolutionSemiconductorMemory1970Fairchild(仙童)Sizeofasinglecorei.e.1bitofmagneticcorestorageHolds256bitsNon-destructivereadMuchfasterthancoreCapacityapproximatelydoubleseachyear1.3AHistoricalSketchofComputerEvolutionMicroprocessors

（微处理器）：40041971FirstmicroprocessorAllCPUcomponentsonasinglechip4bit1.3AHistoricalSketchofComputerEvolutionMicroprocessors

（微处理器）：4004Firstmicroprocessorin1971:Intel4004108kHz,0.06MIPS2300transistors

(10microns)Buswidth:4bitsMemory:640bytes1.3Evolution(计算机发展)

TheFourthGenerationTheFourthGeneration

Followedin1972by80088bitBothdesignedforspecificapplications1974-8080Intel’sfirstgeneralpurposemicroprocessor1.3Evolution(计算机发展)

TheFourthGenerationMicrocomputer:

AppleII1977

SteveJobs,SteveWozniak1.3Evolution(计算机发展)

TheFourthGenerationMicrocomputer:IBMPC1981

Intel8088,4.77MHz1.3Evolution(计算机发展)

TheFourthGenerationMicrocomputer:IBMPCOthers1.3Evolution(计算机发展)

TheFourthGenerationSpeedingitupPipelining

(流水线)OnboardcacheOnboardL1&L2cacheBranchpredictionDataflowanalysisSpeculativeexecution(预测执行)1.4RepresentativeComputerFamiliesPentiumSPARCPowerPC1.4RepresentativeComputerFamiliesPentium4004(1971,4bits,0.108MHz,2300transistorsonachip,640Bmemory)8008(1972,8bits,0.108MHz,3500transistorsonachip,16KBmemory)8080(1974,8bits,2MHz,6000transistorsonachip,64KBmemory)8086(1978,16bits,5~10MHz,29000transistorsonachip,1MBmemory)8088(1979,aslowerandcheaperversionof8086,withsameparameters)80286(1982,16bits,8~12MHz,134000transistorsonachip,16MBmemory)80386(1985,32bits,16~33MHz,275000transistorsonachip,4GBmemory)80486(1989,32bit,25~100MHz,1.2Mtransistors)1.4RepresentativeComputerFamiliesPentiumPentium(1993,32bitsdatapath,64-bitbus,60~233MHz,3.1Mtransistors,2-issuesuperscalarofpipelinedepth=5)Pentiumpro(1995,64bitsdatapath,64-bitbus,150~200MHz,5.5Mtransistors,2-issuesuperscalarofpipelinedepth=12)PentiumⅡ

(1997,32bits,230~400MHz,7.5Mtransistors,PentiumⅡplusMMXinstructions)PentiumⅢ

(1999,64bit1-Gbpssystembus,500~1000MHz,95Mtransistors,SSEinstructions,superscalarprocessorpipelinedepth=10)PentiumⅣ

(2000,64bit32-Gbpssystembus,1.3~1.8GHz,42Mtransistors,MMXandSSEinstructions,superscalarpipelinedepth>=20)ItaniumⅣ(IA-64architecture,6-wide10-stagedeeppipeline)安腾1.4RepresentativeComputerFamiliesSPARCFamilyOriginatedfromSunMicrosystemsCorporationin1987.（工作站）Designedtobemorepowerfulthanordinarypersonalcomputers.Aimingathigh-endapplicationsSUN-1,SUN-2,SUN-31987ScalableProcessorARChitecure(可伸缩体系结构)32-bits,36MHzRISCmachine1995UltraSPARC，64-bitsmachinewith23newinstructionscalledtheVIS(可视信号系统).1.4RepresentativeComputerFamiliesUltraSPARCUltraSPARC-Ⅰ：0.5umCMOS,167MHzUltraSPARC-Ⅱ：0.25um,250~480MHz，apipelineof9stages.UltraSPARC-Ⅲ：0.18um,750~900MHz，apipelineof14stages，4integerexecutionunitsandthreefloating-pointunits,offeringsuper-scalarperformance（超标量性能）.1.4RepresentativeComputerFamiliesPowerPCFamily1990’s,manufacturedbyIBM,MotorolaandAppleFirstusedinIBMRISCSystemRS/6000PowerPC601：1993，32-bitprocessor,50~100MHz，2.8Mtransistors，3independentexecutionunits（integer,floating-point,andbranchprocessing）,for3-issuesuperscalaroperationwithpipelinedepthsequalto4forintegerinstructionsand6forfloating-pointinstruction.PowerPC603：1994，32-bitprocessor，100~300MHz，1.6~2.6Mtransistors，5independentexecutionunits,lowpowerdesign.PowerPC604：1994，32-bitprocessor，166~350MHz，3.6M~5.1Mtransistors，6independentexecutionunits，3integerunits,afloating-pointunit,amemoryload/storeunit,andabranchprocessingunit-for4-issuesuperscalaroperation1.4RepresentativeComputerFamiliesPowerPCFamilyPowerPC620：64-bitprocessor,superscalararchitecturelikethePowerPC604，outoforderexecutionofinstructionsanddynamicbranchprediction,targetedforhigh-endsystems.MPC740/750(G3)：1997，64-bitprocessor，200~366MHz，6.35Mtransistors，integrating2*32KBlevel-1cacheand256KB~1MBlevel-2cacheinthemainprocessorchip.MPC7450(G4)：1999，64-bitprocessor，733MHz，11executionunits-aload/storeunit,abranchunit,4integerunits,afloating-pointunit,and4vectoredoperationunits-for4-issuesuperscalaroperatingwithpipelinedepthequalto7.1.5PerspectivesoftheComputerEvolut