第1章 嵌入式系统与ARM处理器

第1章嵌入式系统与ARM处理器目录处理器的种类1嵌入式系统2ARM处理器3ARM的产品系列4ARM的应用领域51.1嵌入式系统概念嵌入式系统 以应用为中心，以计算机技术为基础，软硬件可裁减，以适应应用系统对功能、可靠性、成本、体积和功耗等有严格要求的专用计算机系统。嵌入式系统组成硬件：微处理器、存储器、I/O接口、输入输出设备。软件：Embedded

RTOS、应用软件。1.2嵌入式系统的硬件组成最小系统电源模块时钟模块复位电路微处理器MPUFlashSDRAMJTAG外设USBLCD键盘串口以太网CAN传感器电机辅助存储器USBLCD键盘串口以太网1.3嵌入式系统的软件结构应用程序Application设备驱动程序Driver硬件（单片机）应用（Application）标准接口函数（API）实时操作系统（RTOS）硬件抽象层（HAL）BSP、驱动硬件（微处理器）不带OS软件结构

带OS软件结构1.4嵌入式系统的特性硬件特性体积小、集成效率高。面向特定的应用。功耗低、电磁兼容性好。软件特性嵌入式软件的开发与硬件紧密相关。软件代码要求高效率和高可靠性。软件一般固化在Flash或Rom中。软件系统具有高实时性。一般采用C语言开发。1.5嵌入式系统设计流程1.需求分析2.体系结构设计3.硬件的设计、制作及测试3.软件的设计、实现及测试4.系统集成5.系统性能测试及可靠性测试6.工业试运行及生产文件准备7.项目总结2.1嵌入式微处理器嵌入式系统上的处理器单元称为嵌入式微处理器。嵌入式微处理器是嵌入式系统硬件的核心、运行嵌入式系统的系统软件和应用软件。嵌入式微处理器处理器内核地址总线数据总线控制类总线片上I/O接口电路时钟、复位电路等通信、控制等模块2.2嵌入式微处理器的种类X86Core

－－Intel公司（工控机）ColdFire－－Motorola（工业控制）PowerPC

－－IBM&Motorola&apple（交换设备）MIPS－－只设计内核的一家美国公司（高性能）ARM－－只设计内核的一家英国公司（一般应用）DSP－－TI（运动控制、算术运算）2.3嵌入式微处理器的特点价格便宜特定的功能体积小能耗低使用方便3.1什么是ARMARM－－AdvancedRISCMachineARM是英国一家电子公司的名字ARM敢为天下先，首创了chipless的生产模式，即该公司既不生产芯片，也不设计芯片，而是设计出高效的IP内核，授权给半导体公司使用。

ARM提供一系列内核、体系扩展、微处理器和系统芯片方案ARM是一种通用的32位RISC处理器ARM是一种功耗很低的高性能处理器3.2ARM公司成立于1990年11月前身为Acorn计算机公司设计ARM系列RISC处理器内核授权ARM内核给生产和销售半导体的合作伙伴ARM公司不生产芯片提供基于ARM架构的开发设计技术软件工具,评估板,调试工具,应用软件,总线架构,外围设备单元，等等3.3ARM合作伙伴3.4ARM处理器的特点体积小、低功耗、低成本、高性能；支持Thumb(16位)和ARM(32位)双指令集；大量使用寄存器，指令执行速度更快；大多数数据操作都在寄存器中完成；寻址方式灵活简单，执行效率高；指令长度固定；对操作系统的支持广泛。4.1ARM处理器的应用领域嵌入式控制汽车、电子设备、保安设备、大容量存储器、调制解调器、打印机。数字消费产品数码相机、数字式电视机、游戏机、GPS、机顶盒、MP4。便携式产品手提式计算机、移动电话、PDA、灵巧电话网络设备VOIP、Wireless、xDSL4.2ARM处理器的应用产品LexmarkZ52ColorJetprinterSamsungML5100AJVC"Pixstar"GC-X1HPJornado820PsionRevoPlusHPCapShareSonyMZ-R90MiniDiscNokia8810NokiaMediamasterNintendo

Gameboy

AdvanceEricssonR380AlbaBushInternetTV3Com10/100PCINICIomegaHipZipDiamondMultimediaRio6005.1ARM

处理器系列

Processorcore ArchitectureARM7TDMIfamily v4TARM720T,ARM740TARM9TDMIfamily

v4TARM920T,ARM922T,ARM940TARM9Efamily v5TE,v5TEJARM946E-S,ARM966E-S,ARM926EJ-SARM10Efamily v5TE,v5TEJARM1020E,ARM1022E,ARM1026EJ-SARM11family v6ARM1136J(F)-S

v6ARM1156T2(F)-S

v6T2ARM1176JZ(F)-S

v6Z5.1ARM

处理器系列CortexMfamily

v7ARMCortex-M0

v7MARMCortex-M3

v7MARMCortex-M4

v7MCortexMfamily

v7ARMCortex-R4

v7RCortexAfamily

v7ARMCortex-A8

v7AARMCortex-A9

v7AARMCortex-A15

v7ACortexA50family

v7ARMCortex-A50 v8A5.2ARM7TDMIfamilyARM7TDMIfeatures3stagepipelineVonNeumannarchitectureCPI~1.9T Thumbinstructionsetsupport32-bitARMinstructions16-bitThumbinstructionsD DebugsupportM Enhancedmultiplier(32x8)withinstructionsfor64-bitresultsI EmbeddedICELogic5.2ARM7TDMIfamily－PipelineAlloperationshereareonregisters(singlecycleexecution)Inthisexampleittakes6clockcyclestoexecute6instructionsClockcyclesperInstruction(CPI)=1CycleOperationADDSUBORRANDEORORR123456789FDEFDEFEFDEFDEDFDEWF-Fetch D

-Decode E-ExecuteM5.3ARM9TDMIfamily5stagepipelineImprovesCPIto~1.5ImprovedmaximumclockfrequencyHarvardarchitectureIncreasesavailablememorybandwidthSimultaneousaccesstoinstructionanddatamemorycanbeachievedNormallysuppliedwithcachesattachedARM922T(pictured)2x8KcachesMemoryManagementUnit(MMU)WriteBufferARM920TAsARM922Tbutwith2x16KcachesARM940THasaMemoryProtectionUnit(MPU)5.3ARM9TDMIfamily－PipelineInstructionFetch

Shift+ALUMemoryAccessRegWriteRegReadRegDecodeFETCHDECODEEXECUTEMEMORYWRITEARM9TDMIARMorThumb

InstDecodeRegSelectRegReadShiftALURegWriteThumb®ARM

decompressARMdecodeInstructionFetchFETCHDECODEEXECUTEARM7TDMI5.4ARM9EfamilyARM9EisbasedontheARM9TDMIcoreCoreimplementationdifferencesArchitectureV5TEsupportSinglecycle32x16multiplierimplementationEmbeddedICELogicRTARM926EJ-S/ARM946E-SConfigurableInstructionandDatacachesInstructionandDataTCMInterfacesAHBbusinterfaceARM926EJ-ShasMMUARM946E-ShasMPUARM966E-SInstructionandDataTCMInterfacesNoCacheorMPU/MMU5.5ARM10EfamilyAnewimplementationoftheARMV5TEarchitectureLongerpipelineforgreaterinstructionthroughput64-bitmemoryinterfacesCorefeaturesArchitecturev5TECPI1.36stagepipelineStaticbranchprediction“Hitundermiss”supportNon-blockingexecutionunit64bitspercycleLDM/STMoperationsEmbeddedICELogicRT-II5.6ARM11family－ARM1136J-SARM1136JF-S(pictured)SynthesizableARMV6ArchitectureHighPerformanceCore8-stagepipelineStaticandDynamicbranchpredictionReturnstackLowlatencyInterruptModePhysically-tagged4-64kI&DCachesInternalConfigurableTCMsFourmainmemoryportsJazelletechnologyIntegratedVFPcoprocessorARM1136J-SAsabovebutwithnoVFP5.6ARM11family－ARM1156T2-SARM1156T2F-S(pictured)AsARM1136JF-SARMv6T2architectureBlended16/32-bitThumb-2Instructionset26%smallerthanARMcode25%fasterthanThumbcodeARM1156T2-SAsabovebutwithnoVFP5.6ARM11family－ARM1176JZ-SARM1176JZF-S(pictured)AsARM1136JF-SARMv6ZarchitectureTrustZonetechnologyParallel“Secureworld”forsensitiveapplicationsARM1176JZ-SAsabovebutwithnoVFP5.7Cortexfamily－M3SWDorJTAGFlashPatch&BreakpointsDataWatchpoints&TraceDebugandSleepControl3-StagePipeline,HarvardArchitecture,Thumb-2ISA(orThumb)30K*Gates1-240ConfigurableInterruptsConfigurablePriorityLevelsNonMaskableInterruptOptionalSerialWireViewer5.7Cortexfamily－M3ARMv7MArchitectureNoARMinstructionsetsupportThumb-2onlyNoCache-NoMMUDebugisoptimizedformicrocontrollerapplicationsVectortableisaddresses,notinstructionsInterruptsautomaticallysave/restorestateExceptionsprogrammedinCNoCoprocessor15Allregistersarememory-mappedInterruptcontrollerispartofCortex-M3macrocell5.7Cortexfamily－R4SynthesizableARMv7-RArchitectureDivideinstructionsSupportforMixedEndiannessUnaligneddatasupportv7DebugArchitectureHighPerformanceCore8-stagepipelineDynamicBranchpredictionReturnstackHardwareDivideNon-maskableinterruptoptionConfigurablecachesandTCMsWithexternalDMAsupport5.7Cortexfamily－A8ProcessorhighlightsHighfrequency,highefficiency,lowpowerIn-order,dual-i