RFID设计综合实例

五、RFID设计实例高频RFID芯片数字控制器框架如下图所示：PPM解码模块接收模拟部分过来的信号，将脉冲位置编码方式的数据解码成数字部分可识别的二进制编码，并将解码后的数据发送到Crccheck模块进行校验，同时发送到Fsm状态机模块对数据指令进行处理。Manchester编码模块则将状态机模块处理完后的数据以及由Crcencode模块产生的Crc检验码一并按照特定格式发送到模拟部分进行调制输出。对于RFID数字部分，一方面，模拟部分过来的信号是随机的，不受时钟信号控制；另一方面，解调信号是不连续的，因此使得解码部分的一部分电路是异步的。将PPM解码模块分为异步模块和解码模块两部分，解码模块由4分频时钟和32分频时钟两个时钟控制。RFID芯片的其余模块都是同步模块，受4分频时钟控制。基于整个数字芯片同步电路和异步电路共存的现象，采取将这两部分分开编译的策略。异步电路只需要编译就够了，因为不可能施加时序约束。将其它同步电路施加合理的时序约束，转换成门级网表以后再和异步电路拼结起来，也就是采取bottom-up的综合策略。特别要注意的是同步和异步模块的接口问题，将异步模块到同步模块的路径设置为伪路径，不考虑它们的时序约束。同时还要注意防止亚稳态，每一个触发器都有规定的建立时间和保持时间参数，在这个参数时间内，时钟的有效沿是不允许变化的，否则得到的结果将是不可知的。采取的措施是在异步和同步的接口之间添加两级触发器，将异步信号同步化。（1）异步模块的综合脚本如下：read_verilogAsync_ctrl.vlinkcurrent_designAsync_ctrlset_operating_condition-minBCCOM-maxWCCOMset_wire_load_model-name8000000set_wire_load_modeenclosedset_drive2[all_inputs]set_load2[all_outputs]compilereport_constraint-all_violatorwrite_sdf-version2.1-contextverilogAsync_test.sdfwrite-fverilog-hierarchy-outputAsync_test.vswrite_test_protocol-formatstil-outAsync_test.spfwrite_sdcAsync_test.sdc（2）同步模块的综合脚本如下（为了节省功耗和面积，同步模块施加了门控时钟）：sethdlin_enable_rtldrc_infotruesetpower_preserve_rtl_hier_namestruesethdlin_no_group_registertrueset_clock_gating_style-sequential_celllatch-setup0.2-hold0.1-control_pointbefore-control_signalscan_enableanalyze-fverilog{Sync_top.vDecoder.vCrc_check.vCrc_encode.vFsm.vEncode_modulate.vEeprom_control.v}elaborateSync_top-gate_clocklinkhookup_testports-verbosereport_clock_gating-gating_elements-gated-ungated-hier>gate.rptuniquifyreset_designcurrent_designSync_topcreate_clock-period296-nameClk_fc4[get_portsClk_fc4]create_clock-period296-namePost_cg_clk4[get_pins-hierarchical"*clk_gate*/ENCLK"]create_clock-period296-namePre_cg_clk4[get_pins-hierarchical"*clk_gate*/CLK"]set_clock_uncertainty1[get_clocksClk_fc4]set_dont_touch_network[get_clocksClk_fc4]set_clock_latency1[get_clocksClk_fc4]set_clock_latency0[get_clocks{Pre_cg_clk4}]set_clock_latency0.7[get_clocks{Post_cg_clk4}]set_clock_transition1[get_clocksClk_fc4]create_clock-period2368-nameClk_fc32[get_portsClk_fc32]create_clock-period2368-namePost_cg_clk32[get_pins-hierarchical"*clk_gate*/ENCLK"]create_clock-period2368-namePre_cg_clk32[get_pins-hierarchical"*clk_gate*/CLK"]set_clock_uncertainty1[get_clocksClk_fc32]set_dont_touch_network[get_clocksClk_fc32]set_clock_latency1[get_clocksClk_fc32]set_clock_latency0[get_clocks{Pre_cg_clk32}]set_clock_latency1[get_clocks{Post_cg_clk32}]set_clock_transition2[get_clocksClk_fc32]set_input_delay150-clockClk_fc4[get_portsData_eeprom]set_input_delay150-clockClk_fc4[get_portsReady_busy]set_output_delay100-clockClk_fc4[get_portsShift_rst]set_output_delay100-clockClk_fc4[get_portsSend_final_out]set_output_delay100-clockClk_fc4[get_portsPpm_sel_ask]set_output_delay100-clockClk_fc4[get_portsEe_addr]set_output_delay100-clockClk_fc4[get_portsData_eeprom]set_output_delay100-clockClk_fc4[get_portsCe]set_output_delay100-clockClk_fc4[get_portsWe]set_output_delay100-clockClk_fc4[get_portsRd]set_output_delay1500-clockClk_fc32[get_portsPresent_EOF_number]set_output_delay1500-clockClk_fc32[get_portsPrevious_EOF_number]set_output_delay1500-clockClk_fc32[get_portsTmp_rst]set_output_delay1500-clockClk_fc32[get_portsData_shift_en]set_output_delay1500-clockClk_fc32[get_portsData_to_async]set_output_delay1500-clockClk_fc32[get_portsQ2n_10_out]set_operating_condition-minBCCOM-maxWCCOMset_wire_load_model-name8000000set_wire_load_modeenclosedset_drive0[listClk_fc4Rst_power_Clk_fc32]set_drive2[listQ1_10_outShift_signalPulse_signalStartup_signalData_eepromReady_busy]set_load1[all_outputs]set_max_area0set_disable_timing[get_portsRst_power_]set_false_path-from[get_clocksClk_fc32]-to[get_clocksClk_fc4]set_false_path-from[get_clocksClk_fc4]-to[get_clocksClk_fc32]set_false_path-from[get_portsStartup_signal]-to[get_clocksClk_fc4]set_false_path-from[get_portsStartup_signal]-to[get_clocksClk_fc32]set_false_path-from[get_portsQ1_10_out]-to[get_clocksClk_fc4]set_false_path-from[get_portsQ1_10_out]-to[get_clocksClk_fc32]set_false_path-from[get_portsPulse_signal]-to[get_clocksClk_fc4]set_false_path-from[get_portsPulse_signal]-to[get_clocksClk_fc32]set_false_path-from[get_portsShift_signal]-to[get_clocksClk_fc4]set_false_path-from[get_portsShift_signal]-to[get_clocksClk_fc32]set_false_path-from[get_portsscan_mode]-to[get_clocksClk_fc4]set_false_path-from[get_portsscan_mode]-to[get_clocksClk_fc32]set_false_path-from[get_portstest_se]-to[get_clocksClk_fc4]set_false_path-from[get_portstest_se]-to[get_clocksClk_fc32]set_false_path-from[get_clocksClk_fc4]-to[get_clocksPre_cg_clk32]set_false_path-from[get_portstest_se]-to[get_clocksPre_cg_clk32]set_false_path-from[get_portstest_se]-to[get_clocksPost_cg_clk32]set_false_path-from[get_portsPulse_signal]-to[get_clocksPre_cg_clk32]set_false_path-from[get_portsStartup_signal]-to[get_clocksPre_cg_clk32]set_false_path-from[get_portsscan_mode]-to[get_clocksPre_cg_clk32]propagate_constraints-gate_clockcompilereport_timing-delaymax>maxdft.rptreport_timing-max_paths100-delaymin>mindft.rptreport_constraint-all_violator>violatordft.rptcheck_scan>check_scan.rptreport_timing_requirements-ignoredwrite_sdf-version2.1-contextverilogSyncgate0316.sdfwrite-fverilog-hierarchy-outputSyncgate0316.vswrite_test_protocol-formatstil-outSyncgate0316.spfwrite_sdcSyncgate0316.sdc（3）将两块分别单独编译以后，再合起来，并对整体模块加扫描链，顶层模块的脚本如下:read_verilog{All_top.vSyncgate0317.vAsync_test.v}linkhookup_testports-verboseuniquifyreset_designcurrent_designAll_topcreate_test_clock-period100-waveform{4555}Clk_fc4create_test_clock-period100-waveform{4555}Clk_fc32set_scan_configuration-bidi_modeoutput-external_tristatesenable_one-chain_count2-clock_mixingno_mixset_test_hold1scan_modeset_signal_typetest_asynch_invertedRst_power_settest_rtldrc_latch_checktransparentcreate_clock-period296-nameClk_fc4[get_portsClk_fc4]set_clock_uncertainty1[get_clocksClk_fc4]set_dont_touch_network[get_clocksClk_fc4]set_clock_latency1[get_clocksClk_fc4]set_clock_transition1[get_clocksClk_fc4]create_clock-period2368-nameClk_fc32[get_portsClk_fc32]set_clock_uncertainty1[get_clocksClk_fc32]set_dont_touch_network[get_clocksClk_fc32]set_clock_latency1[get_clocksClk_fc32]set_clock_transition2[get_clocksClk_fc32]set_input_delay150-clockClk_fc4[get_portsData_eeprom]set_input_delay150-clockClk_fc4[get_portsReady_busy]set_output_delay100-clockClk_fc4[get_portsAddr]set_output_delay100-clockClk_fc4[get_portsData_eeprom]set_output_delay100-clockClk_fc4[get_portsCe]set_output_delay100-clockClk_fc4[get_portsWe]set_output_delay100-clockClk_fc4[get_portsRd]set_output_delay100-clockClk_fc4[get_portsSend_final_out]set_output_delay100-clockClk_fc4[get_portsPpm_sel_ask]set_operating_condition-minBCCOM-maxWCCOMset_wire_load_model-name8000000set_wire_load_modeenclosedset_drive0[listClk_fc4Rst_power_Clk_fc32]set_drive2[listData_10_inData_100_inData_eepromReady_busy]set_load1[all_outputs]set_max_area0set_disable_timing[get_portsRst_power_]set_false_path-from[get_clocksClk_fc32]-to[get_clocksClk_fc4]set_false_path-from[get_clocksClk_fc4]-to[get_clocksClk_fc32]set_false_path-from[get_portstest_se]-to[get_clocksClk_fc4]set_false_path-from[get_portstest_se]-to[get_clocksClk_fc32]set_false_path-from[get_portsscan_mode]-to[get_clocksClk_fc4]set_false_path-from[get_portsscan_mode]-to[get_clocksClk_fc32]set_false_path-from[get_portsData_10_in]-to[get_clocksClk_fc4]set_false_path-from[get_portsData_10_in]-to[get_clocksClk_fc32]set_false_path-from[get_portsData_100_in]-to[get_clocksClk_fc4]set_false_path-from[get_portsData_100_in]-to[get_clocksClk_fc32]settest_default_delay0settest_default_strobe40settest_default_bidir_delay0settest_default_period100set_signal_typetest_scan_in{test_si1test_si2}set_signal_typetest_scan_enabletest_seset_signal_typetest_scan_out{test_so1test_so2}set_scan_pathchain1-clockClk_fc4set_scan_pathchain2-clockClk_fc32compile-scancheck_test>check_test1.rptpreview_scan>preview.rptinsert_scancheck_test>check_test2.rptreport_test-scan_path>scan_path.rptreport_timing-delaymax>maxdft.rptreport_timing-max_paths100-delaymin>mindft.rptreport_constraint-all_violator>violatordft.rptcheck_scan>check_scan.rptreport_timing_requirementsignoredwrite_sdf-version2.1-contextverilogalltest.sdfwrite-fverilog-hierarchy-outputalltest.vswrite_test_proto