数字逻辑设计与应用：Lec02 Digital Circuits

1DigitalLogicDesignandApplication

Lecture#2UESTC,Spring2011Chapter3DigitalCircuitsGiveaknowledgeoftheElectricalaspectsofDigitalCircuits

学习要求2掌握：CMOS逻辑电平和噪声容限；CMOS逻辑基本门的电路结构;理解：CMOS逻辑电路的稳态和动态电气特性；理解：特殊的输入输出电路结构;了解：利用仿真软件对CMOS基本逻辑门的静态特性和动态特性进行仿真。了解：作为电子开关运用的二极管、双极型晶体管、MOS场效应管的工作方式；了解：其他类型的逻辑电路：TTL,ECL等；了解：不同类型、不同工作电压的逻辑电路的输入输出逻辑电平规范值以及它们之间的连接配合的问题。电路成本、速度与基本电路规模的关系。3.1LogicSignalsandGatesDigitlogichidethepitfallsoftheanalogworldbymappingtheinfinitesetofrealvaluesforaphysicalquantityintotwosubsetscorrespondingtojusttwopossiblenumbersorlogic：0an13InfiniteSignaloftherealworldTwovaluesintheDigitalLogicworldlogical

abstraction3.1LogicSignalsandGates4Tab.3-1themapingofpracticalphysicalsignaltothelogicalsignal玩过碟仙、笔仙的游戏吗？3.1LogicSignalsandGates5Bufferamplifier1theminmialinputhighvoltagelevelvoltagelevelWeakstrong3.1LogicSignalsandGates63.1LogicSignalsandGatesMethodsofdescription,analysisanddesigntheabstractlogiccircuitsswitchingalgebraTruthtable/StateTable7X+X=XX*X=X……8AxiomsofLogicAlgebraX=0,ifX1(若X1,则X=0)X=1,ifX0(若X0,则X=1)

0’=1

1’=00·0=0 1+1=11·1=1 0+0=00·1=1·0=0 1+0=0+1=19BasicLogicFunction—AND000010100111ABZLogicEquationZ=A·BSwitch:1-on,0-off

Lamp:1-light,0-unlightedAnANDgateproducesa1outputifandonlyifallitsinputsare1.TruthTable&ABZABZLogicSymbolABZ10BasicLogicFunction:ORLogicEquation

:

Z=A+BABZTruthTableABZAnORgateproducesa1outputifandonlyifoneormoreinputsis1.000011101111≥1ABZABZLogicSymbol

11AZ0110TruthTableLogicEquationZ=A=A’AZRToproduceanoutputvaluethatistheoppositeofitsinputvalue.CommonlycalledanInverter.1ZAAZLogicSymbolBasicLogicFunction:NOT12TruthTable&≥1133.1LogicSignalsandGatesThephysicalaspectsofdigitalcircuitsPhysicalrealizationWorkingprinciplesElectricalcharactersChap.3143.1LogicSignalsandGatesHowtogettheHIGHandLOWVoltage?positivelogic10negativelogic10HighLowConsultFig.3-62forlogicalvoltagecomparetionVOUTVINVccR获得高、低电平的基本原理153.2LogicFamiliesAlogicfamilyisacollectionofdifferentICchipsthathavesimilarinput,output,andinternalcircuitcharacteristics,butthatperformdifferentlogicfunctions.Chipsofsamefamilycanbeconnectedtoperformarbitarylogicfunction.(Fig.6-62)Chipsfromdifferentfamiliesmaynotbecompatible.TTLfamilies(Tab.3-10)CMOSlogic(Fig.3-62)16SomeTermsSemiconductordiode,半导体二极管Bipolarjunctiontransistor,双极结型晶体管Integratedcircuit,集成电路Bipolarlogicfamily,双极型逻辑系列Transistor-transistorlogic,TTL,晶体管-晶体管逻辑Metal-oxidesemiconductorfield-effecttransistor,MOSFET,金属氧化物半导体场效应晶体管ComplementaryMOS,CMOS,互补MOS173.3CMOSLogic1.CMOS

LogicLevelsLogic1(HIGH)

Logic0(LOW)5.0V3.5V1.5V0.0V

undefinedlogiclevel

ACMOSLogicCircuitusesnotonly5-Voltpower-supplyvoltage,butotherpower-supplyvoltages,suchas3.3,2.7volts.182.MOSTransistorsTwoTypes:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsource.192.MOSTransistorsNormally,Vgs>=0IfVgs=0Rds

isveryhigh(>106Ω)

Thetransistoris“Off”.

increaseVgs

decreaseRds

whenRds

isverylow(<=10Ω)

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.202.MOSTransistorsTwoTypes:P-ChannelNormally,

Vgs<=0If

Vgs=0Rds

isveryhigh.

Thetransistoris“Off”.VgsRds

when

Rds

isverylow,

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.注意，空穴的概念，以及空穴导电的实质还是电子导电。2.MOSTransistorsTwoTypesMOS:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsourceRgs、RgdisextremelyhighWhatevervoltageonGate，igs,igd≈0(1µA）iscalledLeakagecurrent.TherearecapacitivecouplingbetweentheGate&Source,Gate&Drain2122BasicMOSon-offCircuitvI+–vO–+iD+VDDRDDGSQ1:CanwereplaceNMOSwithPMOS?Q2:HowtochoosetheloadresistanceRD?IfinputisL,transistoris“off”andoutputisH.

IfinputisH,transistoris“on”,outputisL.

233.BasicCMOSInverterCircuit1.VIN=0.0V(L)VGS1=0.0V，Q1offVGS2=VIN–VDD=–5.0V,Q2onVOUTVDD=5.0V(H)2.VIN=5.0V(H)VGS1=5.0V，Q1onVGS2=VIN–VDD=0.0V,Q2offVOUT0.0V(L)VDD=+5.0VVOUTVINQ2p-channelQ1n-channelGDS2S124VDD=+5.0VVOUTVINQ2p-channelQ1n-channelSwitchmodel25CMOSinverterlogicaloperationVCCVinVoutONwheninputislow

ONwheninputishighVDD=+5.0VVOUTVINQ2p-channelQ1n-channel一个输入同时控制两个MOS管264.CMOSNANDGateUse2ntransistorsforn-inputgate1.Ifbothinputsarehigh,BothQ1andQ3are“on”,BothQ2andQ4are“off”,

Zislow(

0V).2.Ifeitherinputislow,eitherQ1orQ3is“off”,eitherQ2orQ4is“on”,Zishigh(

VDD).VDD=+5.0VZABQ1Q2Q4Q3274.CMOSNANDGateCMOSNAND---moreinputs(3)Can’tbeaddedunlimitedlyFanIn28Thenumberofinputsthatagatehaveiscalledfan-in.Theadditive“on”resistanceofseriestransistorslimitsthefan-inofCMOSgates.Gateswithalargenumberofinputscanbemadebycascading(级联)gateswithfewerinputs.294.CMOSNORGateLikeNAND―2ntransistorsforn-inputgate

1.Ifbothinputsarelow,bothQ1andQ3is“off”,bothQ2andQ4is“on”, Zishigh(VDD).

2.Ifeitherinputishigh,eitherQ1orQ3is“on”,eitherQ2orQ4is“Off”,Zislow(0V).VDD=+5.0VZABQ1Q2Q4Q330NANDvs.NORForagivensiliconarea,PMOStransistorsare“weaker”thanNMOStransistors.Result:NANDgatesarepreferredinCMOS.315.CMOSAOIGatesZ=(A·B+C·D

)’AND-OR-INVERT从NMOS的连接与逻辑“与”、“或”的关系来构造；非是“免费”获得的VDD=+5.0VABZCD325.CMOSAOIGatesZ=(A·B+C·D

)’336.Non-invertingGatesnoninvertingbuffer2-inputANDgateVDD=+5.0VAZIttypicallyisnotpossibletodesignanon-invertinggatewithasmallernumberoftransistorsthananinvertingone.Circuitdiagram:P94Figure3-197.BuildinganarbitarycircuitwithCMOS34每个CMOS门电路都由NMOS和PMOS两部分组成，并且每个输入都同时控制两个管子；NMOS管串联可实现与非操作，并联可实现或非操作；PMOS管正好相反；NMOS管串联时PMOS一定并联；NMOS管并联时PMOS一定串联——对偶关系。PMOS网络和NMOS网络不能同时导通非是“免费”获得的课堂练习

CMOSOAIGates35F=((A+B)·(C+D

))’Fig.3-22课堂练习36Z=(A’+B·C

)’课堂练习37Z=A+B=A’·B+A·B’XORABZ000011101110A’ZBAB’A’ABB’课堂练习38(AOIGates)’Z=A’·B+A·B’=(A’·B+A·B’)’’=((A’·B+A·B’)’)’XORZ=(A·B+C·D

)’393.7OtherCMOSInputandOutputStructures1.TransmissionGatesGates-CMOSTransmissionGatesWhenEN=0,EN_L=1,thetransistorsare“off”,AandBaredisconnected.WhenEN=1,EN_L=0,thetransistorsare“on”,

AandBareconnectedwithalow-impedance.

ENEN_LABBidirectionaldevice双向器件门的导通时延大于传输时延3.7OtherCMOSInputandOutputStructures401.TransmissionGates-NMOS413.7OtherCMOSInputandOutputStructures1.TransmissionGates-PMOS0.1V0V0V0.1V0.1V0.1V0V0.2V0.1V0.2V3.7OtherCMOSInputandOutputStructuresApplicationofTransmissionGates42s’Fig.3-46ZSVCCXYMUX(Multiplexer)s’s’X

YssZ=S’·X+S·Y

010011S=0;T1on,T2off;Z=XS=1;T1off,T2On;Z=Y

ZYXST1T2432.

Three-StateOutputsVCCZENAIfEN=0,C=1,Tp=“off”B=1,D=0,Tn=“off”

Z=Hi-impedancestateor

floatingstateIfEN=1C=A’,B=0,D=A’

Z=A(0or1)BCDTpTnAENOUTLogicSymbol还有很多其他三态缓冲器件类型，其应用主要是三态总线443.

Open-DrainOutputsABZVCCVCC’Rpull-upresistanceABZLogicSymbolAssmallaspossible,tominimizetherisetime.Cannotbearbitrarilysmall,itisdeterminedbyIOLmaxpassivepull-up无源上拉Applications:drivingmultisourcebuses;drivingLEDs;performingwiredlogic.

3.

Open-DrainOutputs45Pull-upresistorvalue上拉电阻阻值的范围ABZVCCRRMin=VCC-VOLMax

iRiR=IOLMax-iLRmax=VCC-VOHMiniRiR=iLeak+iLVout=Rn

Rn+RVCCLH