操作系统第1章习题答案

1.1 Memory(contentsinhex):300:3005;301:5940;302:7006 Step1:3005IR;Step2:3AC Step3:5940IR;Step4:3+2=5AC Step5:7006IR;Step6:ACDevice61.2 1. a. ThePCcontains300,theaddressofthefirstinstruction.ThisvalueisloadedintotheMAR. b. Thevalueinlocation300(whichistheinstructionwiththevalue1940inhexadecimal)isloadedintotheMBR,andthePCisincremented.Thesetwostepscanbedoneinparallel. c. ThevalueintheMBRisloadedintotheIR. 2. a. TheaddressportionoftheIR(940)isloadedintotheMAR. b. Thevalueinlocation940isloadedintotheMBR. c. ThevalueintheMBRisloadedintotheAC. 3. a. ThevalueinthePC(301)isloadedintotheMAR. b. Thevalueinlocation301(whichistheinstructionwiththevalue5941)isloadedintotheMBR,andthePCisincremented. c. ThevalueintheMBRisloadedintotheIR. 4. a. TheaddressportionoftheIR(941)isloadedintotheMAR. b. Thevalueinlocation941isloadedintotheMBR. c. TheoldvalueoftheACandthevalueoflocationMBRareaddedandtheresultisstoredintheAC. 5. a. ThevalueinthePC(302)isloadedintotheMAR. b. Thevalueinlocation302(whichistheinstructionwiththevalue2941)isloadedintotheMBR,andthePCisincremented. c. ThevalueintheMBRisloadedintotheIR. 6. a. TheaddressportionoftheIR(941)isloadedintotheMAR. b. ThevalueintheACisloadedintotheMBR. c. ThevalueintheMBRisstoredinlocation941.1.3 a. 224 b. (1) Ifthelocaladdressbusis32bits,thewholeaddresscanbetransferredatonceanddecodedinmemory.However,sincethedatabusisonly16bits,itwillrequire2cyclestofetcha32-bitinstructionoroperand. (2) The16bitsoftheaddressplacedontheaddressbuscan'taccessthewholememory.Thusamorecomplexmemoryinterfacecontrolisneededtolatchthefirstpartoftheaddressandthenthesecondpart(sincethemicroprocessorwillendintwosteps).Fora32-bitaddress,onemayassumethefirsthalfwilldecodetoaccessa"row"inmemory,whilethesecondhalfissentlatertoaccessa"column"inmemory.Inadditiontothetwo-stepaddressoperation,themicroprocessorwillneed2cyclestofetchthe32bitinstruction/operand. c. Theprogramcountermustbeatleast24bits.Typically,a32-bitmicroprocessorwillhavea32-bitexternaladdressbusanda32-bitprogramcounter,unlesson-chipsegmentregistersareusedthatmayworkwithasmallerprogramcounter.Iftheinstructionregisteristocontainthewholeinstruction,itwillhavetobe32-bitslong;ifitwillcontainonlytheopcode(calledtheopcoderegister)thenitwillhavetobe8bitslong.1.4 Incases(a)and(b),themicroprocessorwillbeabletoaccess216=64Kbytes;theonlydifferenceisthatwithan8-bitmemoryeachaccesswilltransferabyte,whilewitha16-bitmemoryanaccessmaytransferabyteora16-byteword.Forcase(c),separateinputandoutputinstructionsareneeded,whoseexecutionwillgenerateseparate"I/Osignals"(differentfromthe"memorysignals"generatedwiththeexecutionofmemory-typeinstructions);ataminimum,oneadditionaloutputpinwillberequiredtocarrythisnewsignal.Forcase(d),itcansupport28=256inputand281.5 Clockcycle= Buscycle=4125ns=500ns 2bytestransferredevery500ns;thustransferrate=4MBytes/sec Doublingthefrequencymaymeanadoptinganewchipmanufacturingtechnology(assumingeachinstructionswillhavethesamenumberofclockcycles);doublingtheexternaldatabusmeanswider(maybenewer)on-chipdatabusdrivers/latchesandmodificationstothebuscontrollogic.Inthefirstcase,thespeedofthememorychipswillalsoneedtodouble(roughly)nottoslowdownthemicroprocessor;inthesecondcase,the"wordlength"ofthememorywillhavetodoubletobeabletosend/receive32-bitquantities.1.6 a. WhentheCPUhasdatatosendtotheteletype,itchecksFGO.IfFGO=0,theCPUmustwait.IfFGO=1,theCPUtransfersthecontentsoftheACtoOUTRandsetsFGOto0.TheteletypesetsFGIto1afterthewordisprinted. b. Theprocessdescribedin(a)isverywasteful.TheCPU,whichismuchfasterthantheteletype,mustrepeatedlycheckFGIandFGO.Ifinterruptsareused,theteletypecanissueaninterrupttotheCPUwheneveritisreadytoacceptorsenddata.TheIENregistercanbesetbytheCPU(underprogrammercontrol)1.7 Ifaprocessorisheldupinattemptingtoreadorwritememory,usuallynodamageoccursexceptaslightlossoftime.However,aDMAtransfermaybetoorfromadevicethatisreceivingorsendingdatainastream(e.g.,diskortape),andcannotbestopped.Thus,iftheDMAmoduleisheldup(deniedcontinuingaccesstomainmemory),datawillbelost.1.8 Letusignoredataread/writeoperationsandassumetheprocessoronlyfetchesinstructions.Thentheprocessorneedsaccesstomainmemoryonceeverymicrosecond.TheDMAmoduleistransferringcharactersatarateof1200characterspersecond,oroneevery833µs.TheDMAtherefore"steals"every833rdcycle.Thisslowsdowntheprocessorapproximately1.9 a. Theprocessorcanonlydevote5%ofitstimetoI/O.ThusthemaximumI/Oinstructionexecutionrateis106 b. ThenumberofmachinecyclesavailableforDMAcontrolis 106(0.055+0.952)=2.15106 IfweassumethattheDMAmodulecanuseallofthesecycles,andignoreanysetuporstatus-checkingtime,thenthisvalueisthemaximumI/Otransferrate.1.10 a. b. Thetenaccessestoa[i]withintheinnerforloopwhichoccurwithinashortintervaloftime.1.11 Define Ci = Averagecostperbit,memoryleveli Si = Sizeofmemoryleveli Ti = Timetoaccessawordinmemoryleveli Hi = Probabilitythatawordisinmemoryiandinnohigher-levelmemory Bi = Timetotransferablockofdatafrommemorylevel(i+1)tomemoryleveli Letcachebememorylevel1;mainmemory,memorylevel2;andsoon,foratotalofNlevelsofmemory.Then ThederivationofTsismorecomplicated.Webeginwiththeresultfromprobabilitytheorythat: Wecanwrite: WeneedtorealizethatifawordisinM1(cache),itisreadimmediately.IfitisinM2butnotM1,thenablockofdataistransferredfromM2toM1andthenread.Thus: T2=B1+T1 Further T3=B2+T2=B1+B2+T1 Generalizing: So But Finally1.12 a. Cost=Cm8106=8103 b. Cost=Cc8106=8104¢=$800 c. FromEquation1.1: 1.1T1=T1+