集成电路设计 07 时序逻辑设计课件

集成电路设计第七章

时序逻辑电路设计 DesigningSequentialLogicCircuits1EIS-WuhanUniversity集成电路设计第七章时序逻辑电路设计1EIS-WuhanU纲要基本概念组合逻辑与时序逻辑电路有限状态机（FSM）LatchversusRegister锁存器寄存器动态锁存器/寄存器时钟控制寄存器C2MOS流水线非双稳态时序电路时序问题2EIS-WuhanUniversity纲要基本概念2EIS-WuhanUniversityLogicCircuits:

(1)CombinationalLogic (2)SequentialLogic7-1基本概念

3EIS-WuhanUniversityLogicCircuits:7-1基本概念

3EISItismemoryless;i.e.,withoutstates.CombinationalCircuitsInputOutputCombinationalLogic

4EIS-WuhanUniversityItismemoryless;CombinationalCombinationalLogicDesignProcedures1.Constructthetruthtable2.Basedonthetruthtable (a)Simplifythelogicandimplementby (i)randomlogicgates (ii)multiplexers (iii)PLA’sorPAL’s (b)ImplementthecircuitbyROM’s5EIS-WuhanUniversityCombinationalLogicDesignPro——SequentialLogicSequentialLogicAsynchronousCircuitsSynchronousCircuits6EIS-WuhanUniversity——SequentialLogicSequentialLDuetothetimedelayproblems(races,hazards,…etc.)peoplerarelydesignsequentialcircuitsinasynchronousapproach.Synchronouscircuitsneedasystemclocktostrobethewholesystem.Itiseasiertocontroltheinputsandstates.Thespeedmaybeslowerinthesynchronouscircuits.7EIS-WuhanUniversityDuetothetimedelayproblemsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsDQFiniteStateMachine（FSM)8EIS-WuhanUniversityCombinationalclockOutputsStateExternalinputsandstatesastheinputsOutputs，andNextstateClock，edgesensitive（positiveornegative）MealyversusMoorestatemachines9EIS-WuhanUniversityExternalinputsandstatesasMooremachineFF—Flip-Flop

outputdependsonlyonthecurrentstateZ=f(y)potentialimplementationadvantagesinspeedandsize；initialstateFFCombinationalLogicYyXZCLK10EIS-WuhanUniversityMooremachineFFCombinationalMealymachineboththeinputandthecurrentstateisusedtodeterminetheoutput

Z=f(x,y) Y=f(x,y)XyCombinationalCircuitsFFCLKZY11EIS-WuhanUniversityMealymachineXyCombinationalCSixDesign-StepProcessesforFSM1.Understandthestatementofthespecification2.ObtainanabstractspecificationoftheFSM3.Performastateminimization4.Performstateassignment5.ChooseFFtypestoimplementFSMstateregister6.ImplementtheFSM12EIS-WuhanUniversitySixDesign-StepProcessesforStaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower13EIS-WuhanUniversityStaticvsDynamicStorageStatiLatchesvsFlipflopsLatcheslevelsensitivecircuitthatpassesinputstoQwhentheclockishigh(orlow)-transparentmodeinputsampledonthefallingedgeoftheclockisheldstablewhenclockislow(orhigh)-holdmodeFlipflops(edge-triggered)一般指触发器edgesensitivecircuitsthatsampletheinputsonaclocktransitionpositiveedge-triggered:01

negativeedge-triggered:10builtusinglatches(e.g.,master-slaveflipflops)14EIS-WuhanUniversityLatchesvsFlipflopsLatches14ELatchversusRegisterLatch storesdatawhenclockislowRegister storesdatawhenclockrisesDClkQClkDQDClkQClkDQTransparent15EIS-WuhanUniversityLatchversusRegisterLatchRegi7-2锁存器（Latches）类型Latch-BasedDesign时间定义与约束改变输出多路开关型锁存器16EIS-WuhanUniversity7-2锁存器（Latches）类型16EIS-Wuhan类型17EIS-WuhanUniversity类型17EIS-WuhanUniversityLatch-BasedDesign—forsequentialNlatchistransparent

whenf=0Platchistransparent

whenf=1PLatchLogicLogicNLatchf18EIS-WuhanUniversityLatch-BasedDesign—forsequen时间定义（TimingDefinitions）tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQtsuSetup建起时间——时钟翻转之前数据必须有效的时间；thold维持时间——时钟触发之后数据仍然有效的时间；tc-q传播延迟时间——CLK到Q19EIS-WuhanUniversity时间定义（TimingDefinitions）tCLKtCharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q20EIS-WuhanUniversityCharacterizingTimingRegisterL约束（SystemTimingConstraints）约束1： 最小时钟周期：Ttc-q+tplogic+tsu一个CLK周期必须容纳任何一级电路的最大延迟时间tplogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clockperiod)21EIS-WuhanUniversity约束（SystemTimingConstraints）约约束2寄存器维持时间：tholdtcd-register+tcd-logic

tholdtcd-register寄存器最小传播延迟cd---ContaminationDelaytcd-logic逻辑电路最小传播延迟保证时序元件的输入数据在CLK边沿之后能够维持足够的时间，不会因为新进入的数据流而过早改变。tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ22EIS-WuhanUniversity约束2寄存器维持时间：tholdtCLKtDtc-qtholPositiveFeedback:Bi-Stabilitycascadedinverters23EIS-WuhanUniversityPositiveFeedback:Bi-StabilitVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Ifthegaininthetransientregionislargerthan1,onlyAandBarestableoperationpoints.Cisameta-stableoperationpoint.24EIS-WuhanUniversityVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2VMeta-StabilityGainshouldbelargerthan1inthetransitionregion====25EIS-WuhanUniversityMeta-StabilityGainshouldbelBistableCircuits（flip-flops）改变输出cuttingthefeedbackloop(muxbasedlatch)overpoweringthefeedbackloop(asusedinSRAMs)Vi1Vi226EIS-WuhanUniversityBistableCircuits（flip-flopsWritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesbetweenthetransparentandopaquestates弱输出27EIS-WuhanUniversityWritingintoaStaticLatchDCL多路开关型锁存器

（Mux-BasedLatches）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ28EIS-WuhanUniversity多路开关型锁存器

（Mux-BasedLatches）NeMux-BasedLatch传输阶段（透明）维持阶段29EIS-WuhanUniversityMux-BasedLatch传输阶段（透明）29EISMux-BasedLatchNMOSonlyNon-overlappingclocks30EIS-WuhanUniversityMux-BasedLatchNMOSonlyNon-ov7-3寄存器主从式边沿触发寄存器降低时钟负载非理想时钟—时钟重叠静态RS触发器—强信号写数据31EIS-WuhanUniversity7-3寄存器主从式边沿触发寄存器31EIS-WuhanUMaster-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair

32EIS-WuhanUniversityMaster-Slave(Edge-Triggered)Master-SlaveRegisterMultiplexer-basedlatchpair33EIS-WuhanUniversityMaster-SlaveRegisterMultiplex多路开关型寄存器的时序特性寄存器时序参数SetupTime,HoldTime,PropagationDelayassume：反相器传播延迟:tinv传输门传播延迟:tTGClkinverter:

tclk-int=0tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ34EIS-WuhanUniversity多路开关型寄存器的时序特性寄存器时序参数tCLKtDtc-qTimingofRegisterSetupTimeData在Clk上升沿前必须有效的时间—QM稳定时间传播路径：Inv1—

TG1—

Inv3—

TG2Tsetup=

3tinv+tTGPropagationDelayTc-q—

QM传播到输出的时间传播路径：TG3—

Inv6Tc-q=tTG+tinvHoldTimeClk上升沿之后输入必须保持稳定的时间TG1关断Thold=

035EIS-WuhanUniversityTimingofRegisterSetupTime35CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q36EIS-WuhanUniversityCharacterizingTimingRegisterL降低时钟负载（ReducedClockLoad）设计复杂性提高（I2、I4强度）反向传导(可能影响前级存储结果）37EIS-WuhanUniversity降低时钟负载（ReducedClockLoad）设时钟偏差（ClockSkew）

——时钟重叠（ClockOverlap）CLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLK时钟变为上升沿时，从级应为维持状态；由于时钟重叠，D与Q之间形成直接通路；产生竞争：A同时被D、B驱动；减弱B的强度；输出不确定状态。clkskew产生原因？38EIS-WuhanUniversity时钟偏差（ClockSkew）

——时钟重叠（Clo伪静态两相D寄存器——不重叠时钟两相时钟；时间间隔足够长；伪静态—保持时间长，漏电影响；不会产生重叠。CLK1CLK1ABXDQCLK2CLK2CLK2CLK139EIS-WuhanUniversity伪静态两相D寄存器——不重叠时钟两相时钟；CLK1CLK1A静态RS触发器—强信号写数据（OverpoweringtheFeedbackLoop

─Cross-CoupledPairs）NOR-basedset-reset40EIS-WuhanUniversity静态RS触发器—强信号写数据（OverpoweringthCross-CoupledNANDCross-coupledNANDsAddedclockThisisnotusedindatapathsanymore,

butisabasicbuildingmemorycell41EIS-WuhanUniversityCross-CoupledNANDCross-couple7-4动态锁存器/寄存器DCLKCLKQDynamic(charge-based)StaticStorageMechanisms42EIS-WuhanUniversity7-4动态锁存器/寄存器DCLKCLKQDynamic(StaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower43EIS-WuhanUniversityStaticvsDynamicStorageStati动态边沿触发寄存器CLKCLKQDCLKCLKSetupTime传播路径：TG1Tsetup=tTG

PropagationDelay传播路径：Inv1—TG2—Inv3Tc-q=tTG+2tinv

HoldTimeThold=044EIS-WuhanUniversity动态边沿触发寄存器CLKCLKQDCLKCLKSetupTMakingaDynamicLatchPseudo-Static针对噪声干扰和漏电影响；伪静态—弱反馈；增加延时，提高抗干扰能力。45EIS-WuhanUniversityMakingaDynamicLatchPseudo-7-5时钟控制寄存器C2MOS

——时钟偏差不敏感方法“Keepers”canbeaddedtomakecircuitpseudo-static主从式；正沿触发；CLK=0时X=D求值，从级维持（高阻态）；CLK=1时相反。只要时钟边沿的上升和下降时间足够小，对时钟重叠不敏感。46EIS-WuhanUniversity7-5时钟控制寄存器C2MOS

——时钟偏差不敏感方InsensitivetoClock-OverlapM1DQM4M200VDDXM5M8M6VDD(a)(0-0)overlapM3M1DQM21VDDXM71M5M6VDD(b)(1-1)overlap47EIS-WuhanUniversityInsensitivetoClock-OverlapM17-6真单相时钟寄存器

（TrueSinglePhaseClockRegister）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)无时钟重叠；减少时钟负载。48EIS-WuhanUniversity7-6真单相时钟寄存器

（TrueSinglePhasIncludingLogicinTSPCANDlatchExample:logicinsidethelatch可嵌入逻辑功能。49EIS-WuhanUniversityIncludingLogicinTSPCANDlatTSPCRegisterCLK=0X=反相的D，Y预充电，Q维持；CLK=1X高阻，Y=X的反相，Q=Y。50EIS-WuhanUniversityTSPCRegisterCLK=050EIS-WuhanPulse-TriggeredLatchesMaster-SlaveLatchesDClkQDClkQClkDataDClkQClkDataPulse-TriggeredLatchL1L2LWaystodesignanedge-triggeredsequentialcell:51EIS-WuhanUniversityPulse-TriggeredLatchesMaster-PulsedLatches52EIS-WuhanUniversityPulsedLatches52EIS-WuhanUniv7-7流水线（Pipelining）ReferencePipelined寄存器传播延迟寄存器建立时间组合逻辑最坏延迟53EIS-WuhanUniversity7-7流水线（Pipelining）ReferencePiLatch-BasedPipeline54EIS-WuhanUniversityLatch-BasedPipeline54EIS-Wuha7-8非双稳态时序电路

Non-BistableSequentialCircuitsSchmittTriggerMonostableTriggerAstableMultivibratorsVCO55EIS-WuhanUniversity7-8非双稳态时序电路

Non-BistableSequSchmittTrigger对于缓慢的输入，快速翻转的输出响应；VTC正向、负向变化的输入信号有不同的阈值；滞回电压为其差；用于提高抗干扰能力，减少振铃现象。InOutVinVoutVOHVOLVM–VM+56EIS-WuhanUniversitySchmittTrigger对于缓慢的输入，快速翻转的输出NoiseSuppressionusingSchmittTrigger57EIS-WuhanUniversityNoiseSuppressionusingSchmitCMOSSchmittTriggerMovesswitchingthresholdofthefirstinverter反相器等效晶体管比：β1/（β

2+β

4）开关阈值提高反相器等效晶体管比：（β

1+β

3）/β2开关阈值降低58EIS-WuhanUniversityCMOSSchmittTriggerMovesswitMultivibratorCircuitsBistableMultivibratorMonostableMultivibratorAstableMultivibratorflip-flop,SchmittTriggerone-shotoscillatorSRT59EIS-WuhanUniversityMultivibratorCircuitsBistableTransition-TriggeredMonostableDELAYtdInOuttd60EIS-WuhanUniversityTransition-TriggeredMonostablMonostableTrigger(RC-based)VDDInOutABCRInBOuttVMt2t1(a)Triggercircuit.(b)Waveforms.61EIS-WuhanUniversityMonostableTrigger(RC-based)VAstableMultivibrators(Oscillators)RingOscillator奇数个反相器T=2N*tpsimulatedresponseof5-stageoscillator012N-162EIS-WuhanUniversityAstableMultivibrators(OscillRelaxationOscillator—弛缓Out2CROut1IntI1I2T=2(log3)RCanoscillatorinwhichacapacitorischargedgraduallyandthendischargedrapidly63EIS-WuhanUniversityRelaxationOscillator—弛缓Out2CRVoltageControllerOscillator(VCO)InVDDM3M1M2M4M5VDDM6VcontrCurrentstarvedinverterIrefIrefSchmittTriggerrestoressignalslopesVcontr

(V)0.0246tpHL

(nsec)propagationdelayasafunctionofcontrolvoltage64EIS-WuhanUniversityVoltageControllerOscillatorDifferentialDelayElementandVCOin2twostageVCOv1v2v3v4VctrlVo2Vo1in1delaycell

simulatedwaveformsof2-stageVCO0.50.00.51.01.52.02.53.020.51.5V1V2V3V4time(ns)2.53.565EIS-WuhanUniversityDifferentialDelayElementand7-9时序问题

——数据路径（Datapath）设计基本问题时序逻辑静态与动态存储同步/异步时钟偏差与抖动来源时钟偏差时钟抖动时钟分布网络时钟技术设计准则66EIS-WuhanUniversity7-9时序问题

——数据路径（Datapath）设计基本Review:SequentialDefinitions寄存器两个电平触发latches

ofoppositetypemaster-slavechangesstateonaclockedge67EIS-WuhanUniversityReview:SequentialDefinitionStaticstorage——Dynamicstorage

Staticstorage双稳态——bistable反馈——withfeedbacktostoreitsstate保持——preservesstateaslongasthepowerison更新数据cuttingthefeedbackpath(muxbased);overpoweringthefeedbackpath(SRAMbased)Dynamicstorage寄生电容——parasiticcapacitorsonlyaperiodoftime(milliseconds)刷新——periodicrefreshfewertransistorshigherspeedlowerpower伪静态pseudostaticduetonoise68EIS-WuhanUniversityStaticstorage——DynamicstoragTimingClassifications同步系统（Synchronoussystems）所有存储单元同步更新使用同步clocksignalstrictconstraintsontheclocksignalgenerationanddistributiontominimize时钟偏差Clockskew(spatialvariationsinclockedges)时钟抖动Clockjitter(temporalvariationsinclockedges)异步系统（Asynchronoussystems）自定时Self-timedsystems不需要全局时钟globallydistributedclock握手协议控制handshaking69EIS-WuhanUniversityTimingClassifications同步系统（SynSynchronousTimingBasicsUnderidealconditions(i.e.,whentclk1=tclk2)Ttc-q+tplogic+tsuthold

≤tcdlogic+tcdregUnderrealconditionsskewisconstantfromcycletocycleskewcanbepositiveornegativejittercausesTtochangeonacycle-by-cyclebasisDQR1CombinationallogicDQR2clkIntclk1tclk2tc-q,tsu,thold,tcdregtplogic,tcdlogic70EIS-WuhanUniversitySynchronousTimingBasicsUnderSourcesofClockSkewandJitterinClockNetworkPLL1243567clockgenerationclockdriverspowersupplyinterconnectcapacitiveloadcapacitivecouplingtemperatureSkewmanufacturingdevicevariationsinclockdriversinterconnectvariationsenvironmentalvariations(powersupplyandtemperature)Jitterclockgenerationcapacitiveloadingandcouplingenvironmentalvariations(powersupplyandtemperature)71EIS-WuhanUniversitySourcesofClockSkewandJittPositiveClockSkew>0:Improvesperformance,butmakestholdhardertomeet.Iftholdisnotmet(raceconditions).T+

tc-q+tplogic+tsusoTtc-q+tplogic+tsu-thold+≤tcdlogic+tcdregsothold≤tcdlogic+tcdreg-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+>0+thold123472EIS-WuhanUniversityPositiveClockSkew>0:ImprNegativeClockSkewClockanddataflowinoppositedirectionsT+

tc-q+tplogic+tsusoTtc-q+tplogic+tsu-thold+≤tcdlogic+tcdregsothold≤tcdlogic+tcdreg-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+<01234<0:Degradesperformance,butthold

iseasiertomeet73EIS-WuhanUniversityNegativeClockSkewClockanddClockJitterJittercausesTtovaryonacycle-by-cyclebasisR1CombinationallogicclkIntclkT-tjitter+tjitterT-2tjitter

tc-q+tplogic+tsuTtc-q+tplogic+tsu+2tjitterJitterdirectlyreducestheperformanceofasequentialcircuit74EIS-WuhanUniversityClockJitterJittercausesTtoCombinedImpactofSkewandJitterConstraintsontheminimumclockperiod(>0)DQR1CombinationallogicDQR2Intclk1tclk2TT+>01612-tjitterTtc-q+tplogic+tsu-+2tjitter

thold≤tcdlogic+tcdreg––2tjitter75EIS-WuhanUniversityCombinedImpactofSkewandJiClockDistributionNetworksClockskewandjitter影响性能消耗能量dynamicpower应支持时钟控制clockgating(shuttingdownunits)时钟分布技术ClockdistributionBalancedpaths(H-treenetwork,matchedRCtrees)Intheidealcase,caneliminateskewCouldtakemultiplecyclesfortheclocksignaltopropagatetotheleavesofthetreeClockgridsTypicallyusedinthefinalstageoftheclockdistributionnetworkMinimizesabsolutedelay(notrelativedelay)76EIS-WuhanUniversityClockDistributionNetworksCloH-TreeClockNetworkClockClockIdleconditionGatedclockIfthepathsareperfectlybalanced,clockskewiszero;Caninsertclockgatingatmultiplelevelsinclocktree;Canshutoffentiresubtreeifallgatingconditionsaresatisfied.77EIS-WuhanUniversityH-TreeClockNetworkClockClockDECAlpha21164(EV5)300MHzclock(9.3milliontransistorsona16.5x18.1mmdiein0.5micronCMOStechnology)singlephaseclock3.75nFtotalclockloadExtensiveuseofdynamiclogic20W(outof50)inclockdistributionnetworkTwolevelclockdistributionSingle6stagedriveratthecenterofthechipSecondarybuffersdrivetheleftandrightsidesoftheclockgridinm3andm4Totalequivalentdriversize(宽度)of58cm!!78EIS-WuhanUniversityDECAlpha21164(EV5)300MHzc79EIS-WuhanUniversity79EIS-WuhanUniversityClockSkewinAlphaProcessorAbsoluteskewsmallerthan90psThecriticalinstructionandexecutionunitsallseetheclockwithin65ps80EIS-WuhanUniversityClockSkewinAlphaProcessorADealingwithClockSkewandJitterTominimizeskew,balanceclockpathsusingH-treeormatched-treeclockdistributionstructures.Ifpossible,routedataandclockinoppositedirections;eliminatesracesatthecostofperformance.Theuseofgatedclockstohelpwithdynamicpowerconsumptionmakejitterworse.Shieldclockwires(routepowerlines–VDDorGND–nexttoclocklines)tominimize/eliminatecouplingwithneighboringsignalnets.改善层间绝缘介质一致性Usedummyfillstoreduceskewbyreducingvariationsininterconnectcapacitancesduetointerlayerdielectricthicknessvariations.Powersupplynoisefundamentallylimitstheperformanceofclocknetworks.81EIS-WuhanUniversityDealingwithClockSkewandJi集成电路设计第七章

时序逻辑电路设计 DesigningSequentialLogicCircuits82EIS-WuhanUniversity集成电路设计第七章时序逻辑电路设计1EIS-WuhanU纲要基本概念组合逻辑与时序逻辑电路有限状态机（FSM）LatchversusRegister锁存器寄存器动态锁存器/寄存器时钟控制寄存器C2MOS流水线非双稳态时序电路时序问题83EIS-WuhanUniversity纲要基本概念2EIS-WuhanUniversityLogicCircuits:

(1)CombinationalLogic (2)SequentialLogic7-1基本概念

84EIS-WuhanUniversityLogicCircuits:7-1基本概念

3EISItismemoryless;i.e.,withoutstates.CombinationalCircuitsInputOutputCombinationalLogic

85EIS-WuhanUniversityItismemoryless;CombinationalCombinationalLogicDesignProcedures1.Constructthetruthtable2.Basedonthetruthtable (a)Simplifythelogicandimplementby (i)randomlogicgates (ii)multiplexers (iii)PLA’sorPAL’s (b)ImplementthecircuitbyROM’s86EIS-WuhanUniversityCombinationalLogicDesignPro——SequentialLogicSequentialLogicAsynchronousCircuitsSynchronousCircuits87EIS-WuhanUniversity——SequentialLogicSequentialLDuetothetimedelayproblems(races,hazards,…etc.)peoplerarelydesignsequentialcircuitsinasynchronousapproach.Synchronouscircuitsneedasystemclocktostrobethewholesystem.Itiseasiertocontroltheinputsandstates.Thespeedmaybeslowerinthesynchronouscircuits.88EIS-WuhanUniversityDuetothetimedelayproblemsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsDQFiniteStateMachine（FSM)89EIS-WuhanUniversityCombinationalclockOutputsStateExternalinputsandstatesastheinputsOutputs，andNextstateClock，edgesensitive（positiveornegative）MealyversusMoorestatemachines90EIS-WuhanUniversityExternalinputsandstatesasMooremachineFF—Flip-Flop

outputdependsonlyonthecurrentstateZ=f(y)potentialimplementationadvantagesinspeedandsize；initialstateFFCombinationalLogicYyXZCLK91EIS-WuhanUniversityMooremachineFFCombinationalMealymachineboththeinputandthecurrentstateisusedtodeterminetheoutput

Z=f(x,y) Y=f(x,y)XyCombinationalCircuitsFFCLKZY92EIS-WuhanUniversityMealymachineXyCombinationalCSixDesign-StepProcessesforFSM1.Understandthestatementofthespecification2.ObtainanabstractspecificationoftheFSM3.Performastateminimization4.Performstateassignment5.ChooseFFtypestoimplementFSMstateregister6.ImplementtheFSM93EIS-WuhanUniversitySixDesign-StepProcessesforStaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower94EIS-WuhanUniversityStaticvsDynamicStorageStatiLatchesvsFlipflopsLatcheslevelsensitivecircuitthatpassesinputstoQwhentheclockishigh(orlow)-transparentmodeinputsampledonthefallingedgeoftheclockisheldstablewhenclockislow(orhigh)-holdmodeFlipflops(edge-triggered)一般指触发器edgesensitivecircuitsthatsampletheinputsonaclocktransitionpositiveedge-triggered:01

negativeedge-triggered:10builtusinglatches(e.g.,master-slaveflipflops)95EIS-WuhanUniversityLatchesvsFlipflopsLatches14ELatchversusRegisterLatch storesdatawhenclockislowRegister storesdatawhenclockrisesDClkQClkDQDClkQClkDQTransparent96EIS-WuhanUniversityLatchversusRegisterLatchRegi7-2锁存器（Latches）类型Latch-BasedDesign时间定义与约束改变输出多路开关型锁存器97EIS-WuhanUniversity7-2锁存器（Latches）类型16EIS-Wuhan类型98EIS-WuhanUniversity类型17EIS-WuhanUniversityLatch-BasedDesign—forsequentialNlatchistransparent

whenf=0Platchistransparent

whenf=1PLatchLogicLogicNLatchf99EIS-WuhanUniversityLatch-BasedDesign—forsequen时间定义（TimingDefinitions）tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQtsuSetup建起时间——时钟翻转之前数据必须有效的时间；thold维持时间——时钟触发之后数据仍然有效的时间；tc-q传播延迟时间——CLK到Q100EIS-WuhanUniversity时间定义（TimingDefinitions）tCLKtCharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q101EIS-WuhanUniversityCharacterizingTimingRegisterL约束（SystemTimingConstraints）约束1： 最小时钟周期：Ttc-q+tplogic+tsu一个CLK周期必须容纳任何一级电路的最大延迟时间tplogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clockperiod)102EIS-WuhanUniversity约束（SystemTimingConstraints）约约束2寄存器维持时间：tholdtcd-register+tcd-logic

tholdtcd-register寄存器最小传播延迟cd---ContaminationDelaytcd-logic逻辑电路最小传播延迟保证时序元件的输入数据在CLK边沿之后能够维持足够的时间，不会因为新进入的数据流而过早改变。tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ103EIS-WuhanUniversity约束2寄存器维持时间：tholdtCLKtDtc-qtholPositiveFeedback:Bi-Stabilitycascadedinverters104EIS-WuhanUniversityPositiveFeedback:Bi-StabilitVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Ifthegaininthetransientregionislargerthan1,onlyAandBarestableoperationpoints.Cisameta-stableoperationpoint.105EIS-WuhanUniversityVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2VMeta-StabilityGainshouldbelargerthan1inthetransitionregion====106EIS-WuhanUniversityMeta-StabilityGainshouldbelBistableCircuits（flip-flops）改变输出cuttingthefeedbackloop(muxbasedlatch)overpoweringthefeedbackloop(asusedinSRAMs)Vi1Vi2107EIS-WuhanUniversityBistableCircuits（flip-flopsWritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesbetweenthetransparentandopaquestates弱输出108EIS-WuhanUniversityWritingintoaStaticLatchDCL多路开关型锁存器

（Mux-BasedLatches）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ109EIS-WuhanUniversity多路开关型锁存器

（Mux-BasedLatches）NeMux-BasedLatch传输阶段（透明）维持阶段110EIS-WuhanUniversityMux-BasedLatch传输阶段（透明）29EISMux-BasedLatchNMOSonlyNon-overlappingclocks111EIS-WuhanUniversityMux-BasedLatchNMOSonlyNon-ov7-3寄存器主从式边沿触发寄存器降低时钟负载非理想时钟—时钟重叠静态RS触发器—强信号写数据112EIS-WuhanUniversity7-3寄存器主从式边沿触发寄存器31EIS-WuhanUMaster-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair

113EIS-WuhanUniversityMaster-Slave(Edge-Triggered)Master-SlaveRegisterMultiplexer-basedlatchpair114EIS-WuhanUniversityMaster-SlaveRegisterMultiplex多路开关型寄存器的时序特性寄存器时序参数SetupTime,HoldTime,PropagationDelayassume：反相器传播延迟:tinv传输门传播延迟:tTGClkinverter:

tclk-int=0tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ115EIS-WuhanUniversity多路开关型寄存器的时序特性寄存器时序参数tCLKtDtc-qTimingofRegisterSetupTimeData在Clk上升沿前必须有效的时间—QM稳定时间传播路径：Inv1—

TG1—

Inv3—

TG2Tsetup=

3tinv+tTGPropagationDelayTc-q—

QM传播到输出的时间传播路径：TG3—

Inv6Tc-q=tTG+tinvHoldTimeClk上升沿之后输入必须保持稳定的时间TG1关断Thold=

0116EIS-WuhanUniversityTimingofRegisterSetupTime35CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q117EIS-WuhanUniversityCharacterizingTimingRegisterL降低时钟负载（ReducedClockLoad）设计复杂性提高（I2、I4强度）反向传导(可能影响前级存储结果）118EIS-WuhanUniversity降低时钟负载（ReducedClockLoad）设时钟偏差（ClockSkew）

——时钟重叠（ClockOverlap）CLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLK时钟变为上升沿时，从级应为维持状态；由于时钟重叠，D与Q之间形成直接通路；产生竞争：A同时被D、B驱动；减弱B的强度；输出不确定状态。clkskew产生原因？119EIS-WuhanUniversity时钟偏差（ClockSkew）

——时钟重叠（Clo伪静态两相D寄存器——不重叠时钟两相时钟；时间间隔足够长；伪静态—保持时间长，漏电影响；不会产生重叠。CLK1CLK1ABXDQCLK2CLK2CLK2CLK1120EIS-WuhanUniversity伪静态两相D寄存器——不重叠时钟两相时钟；CLK1CLK1A静态RS触发器—强信号写数据（OverpoweringtheFeedbackLoop

─Cross-CoupledPairs）NOR-basedset-reset121EIS-WuhanUniversity静态RS触发器—强信号写数据（OverpoweringthC