海思3559A pwm驱动编写记录

1、由于hisi3559a的内核中未包含pwm驱动，故需自己编写。.修改Kconfig文件翻开XXX/drivers/pwm文件夹(XXX代表内核路径)中的Kconfig文件 增加如下 内容config PWM.HISItristate hisi3559a PWM support by zd zjhhelpGeneric PWM framework driver for hisi3559a by zd zjh.这样在menuconfig中将增加对应的选项.修改 makefile翻开XXX/drivers/pwm文件夹(XXX代表内核路径)中的Makefile文件增加如下内容obj-$(CONFIG

2、_PWM_HISI)+ 二 pwm-hisi.o即根据menuconfig中是否选择PWM_HISI来决定是否编译我们将要添加的驱动程 序。.编写pwm驱动在XXX/drivers/pwm文件夹中新增pwm-hisi.c文件编写内容为：/*Driver for hisi3559a Pulse Width Modulation Controller*Copyright (C) 2021 zjh *Licensed under GPLv2./#include #include compatible = hisilicon,hi-pwm;reg = ;clocks = ;#pwm-cells = ;

3、clock-names = apb_pclk;status =disabled;)：pwm2: pwm0 xl80900E0 compatible = hisilicon,hi-pwm;reg = ;clocks = ;#pwm-cells = ;clock-names = apb_pclk;status = disabled;)；可以看到，上面的clocks项和时钟驱动中修改的内容是相关联的。6.应用层使用例如(Qt)#include#include#include#include#includeQDebug#includeint exportPwm(unsigned int pwm)(in

4、t fd = -1;std:string sPath;if (pwm 3)(sPath = /sys/class/pwm/pwmchip + std:to_string(pwm) + /export;fd = open(sPath.c_str(), O_WRONLY);if (fd 0) TOC o 1-5 h z (printf(open export failedn);return -1;write(fd, 0,2);close(fd);return 0;elsereturn -1;int configPwm(unsigned int pwm, unsigned int period, u

5、nsigned int duty_cycle)(int fd = 0, len_p = 0, len_d = 0;char buf_p32;char buf_d32;std:string sPath;Ien_p = snprintf(buf_p, sizeof(buf_p), %d, period);Ien_d = snprintf(buf_d, sizeof(buf_d), %d, duty_cycle);if (pwm 3)(sPath = 7sys/class/pwm/pwmchip + std:to_string(pwm) + /pwmO/period;fd = open(sPath.

6、c_str(), O_WRONLY);if (fd 0)(printf(open period failedn);return -1;write(fd,buf_p, len_p);close(fd);sPath=7sys/class/pwm/pwmchip+ std:to_string(pwm) +7pwm0/duty_cycle;fd =open(sPath.c_str(),O_WRONLY); TOC o 1-5 h z if (fd0)printf(open duty_cycle failedn);return -1;write(fd, buf_d, len_d);close(fd);r

7、eturn 0;elsereturn -1;int enablePwm(unsigned int pwm)(int fd = 0;std:string sPath;if (pwm 3)sPath = /sys/class/pwm/pwmchip + std:to_string(pwm) + /pwmO/enable;fd = open(sPath.c_str(),O_WRONLY);if (fd 0)(printf(open enable failedn);return -1;write(fd, 1, 2);close(fd);return 0;elsereturn -1;int disabl

8、ePwm(unsigned int pwm)int fd = 0;std:string sPath;if (pwm 3)(sPath = /sys/class/pwm/pwmchip + std:to_string(pwm) + /pwmO/enable;fd = open(sPath.c_str(),O.WRONLY);if (fd 0)(printf(open enable failedn);return -1;write(fd, 0, 2);close(fd);return 0;)elsereturn -1;void setDefalutLumia(void)(int i = expor

9、tPwm(O);if (i != 0)qDebug() pwm export failed!;configPwm(0, 750, 375);enablePwm(O);void initFanPWM(void)int i = exportPwm(l);if (i != 0)qDebug() pwml export failed!;i = exportPwm(2);if (i != 0)qDebug() #includeinux/io.h#includeinux/module.h#includeinux/of.h#includeinux/of device.h#include#include#in

10、cludeinux/platform_device.h inux/pwm.h inux/slab.h#include#includeinux/spinlock.h inux/time.h/寄存器偏移量#include#include0 x00 0 x04 0 x08 OxOC 0 x10 0 x14 0 x18 BIT(O) BIT(l) BIT(2)#define PWM_CFG0#define PWM_CFG10 x00 0 x04 0 x08 OxOC 0 x10 0 x14 0 x18 BIT(O) BIT(l) BIT(2)#define PWM_CFG2#define PWM_CT

11、RL#define PWM_STATEO#define PWM_STATE1#define PWM_STATE2#define PWM_EN#define PWMJNV#define PWM_KEEP struct hisi_pwm_data /bool has_prescaler_bypass;/bool has_rdy;unsigned int npwm;);struct hisi_pwm_chip struct pwm_chip chip;struct elk *clk;void _iomem *base;spinlock_t ctrljock;const struct hisi_pwm

12、_data *data;);static inline struct hisi_pwm_chip *to_hisi_pwm_chip(struct pwm_chip *chip) (return container_of(chip, struct hisi_pwm_chip, chip);)/读寄存器static inline u32 hisi_pwm_readl(struct hisi_pwm_chip *chip, unsigned long offset)( return readl(chip-base + offset);)/写寄存器static inline void hisi_pw

13、m_writel(struct hisi_pwm_chip *chip, u32 val, unsigned long offset)( writel(val, chip-base + offset);/配置pwmstatic int hisi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns)(struct hisi_pwm_chip *hisi_pwm 二 to_hisi_pwm_chip(chip); u32 val = 0;u64 clk_rate = 0; int

14、err;clk_rate = clk_get_rate(hisi_pwm-clk); printk(KERN_CRIT pwm elk rate: %lldn, clk_rate);err = clk_prepare_enable(hisi_pwm-clk); if (err) dev_err(chip-dev, failed to enable PWM clockn); return err;spin_lock(&hisLpwm-ctrl_lock);/val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);/val &二 OxFFFE;/hisi_pwm_writ

15、el(hisi_pwm, val, PWM_CTRL);/val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);/val &二 OxFFFB; /hisLpwm_writel(hisLpwm, val, PWM_CTRL);Ado ( val = hisLpwm_readl(hisi_pwm, PWM_STATE2); printk(KERN_CRIT wait for pwm idle.An);)while(0 x400 = (val & 0 x400);*/if (duty_ns = 1)(hisi_pwm_writel(hisLpwm, duty_ns, PW

16、M_CFG1);printk(KERN_CRIT duty reg have be written.An);)if (period_ns = 2)(hisi_pwm_writel(hisLpwm, period_ns, PWM_CFG0);printk(KERN_CRIT period reg have be written.An);)/hisi_pwm_writel(hisi_pwm, Oxa, PWM_CFG2);printk(KERN_CRIT num reg have be written.An);/val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);/v

17、al &二 OxFFFE;/hisi_pwm_writel(hisi_pwm, val, PWM_CTRL);val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);val |= 0 x05;hisi_pwm_writel(hisi_pwm, val, PWM_CTRL);spin_unlock(&hisi_pwm-ctrl_lock);clk_disable_unprepare(hisLpwm-clk);return 0;)static int hisi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_devic

18、e *pwm, enum pwm_polarity polarity)(struct hisi_pwm_chip *hisi_pwm = to_hisi_pwm_chip(chip);u32 val;int ret;ret = clk_prepare_enable(hisi_pwm-clk);if (ret) dev_err(chip-dev, failed to enable PWM clockn);return ret;spin_lock(&hisi_pwm-ctrl_lock);val = hisLpwm_readl(hisLpwm, PWM_CTRL);if (polarity !=

19、PWM_POLARITY_NORMAL)val |= 0 x02;elseval &二 OxFFFD;hisLpwm_writel(hisi_pwm, val, PWM_CTRL);spin_unlock(&hisi_pwm-ctrlock);clk_disable_unprepare(hisi_pwm-clk);return 0;)static int hisi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)(struct hisi_pwm_chip *hisi_pwm = to_hisi_pwm_chip(chip);u3

20、2 val;int ret;ret = clk_prepare_enable(hisi_pwm-clk);if (ret) dev_err(chip-dev, failed to enable PWM clockn); return ret;spin_lock(&hisLpwm-ctrl_lock);val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);val |= 0 x05;hisi_pwm_writel(hisi_pwm, val, PWM_CTRL);spin_unlock(&hisi_pwm-ctrl_lock);return 0;)static void

21、 hisi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)struct hisi_pwm_chip *hisi_pwm = to_hisi_pwm_chip(chip);u32 val;spinjock(&hisi_pwm-ctrl_lock);val = hisi_pwm_readl(hisi_pwm, PWM_CTRL);val &二 OxFFFE;hisLpwm_writel(hisi_pwm, val, PWM_CTRL);spin_unlock(&hisi_pwm-ctrl_lock);clk_disable_un

22、prepare(hisi_pwm-clk); )static const struct pwm_ops hisi_pwm_ops = .config = hisi_pwm_config, ,set_polarity = hisi_pwm_set_polarity, .enable = hisi_pwm_enable, .disable = hisi_pwm_disable, .owner = THIS_MODULE,);static const struct hisi_pwm_data hisi_pwm_data_l = /.has_prescaler_bypass = true, /.has

23、_rdy = true, ,npwm = 1,);static const struct of_device_id hisi_pwm_of_match = patible = hisilicon,hi-pwm, .data = &hisi_pwm_data_l, ()；MODULE_DEVICE_TABLE(of, hisi_pwm_of_match);static int hisi_pwm_probe(struct platform_device *pdev) (struct hisi_pwm_chip *pwm;struct resource *res;int ret;const stru

24、ct of_device_id *match;match = of_match_device(hisLpwm_of_match, &pdev-dev);pwm = devm_kzalloc(&pdev-dev, sizeof(*pwm), GFP_KERNEL); if (!pwm)return -ENOMEM;res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pwm-base = devm_ioremap_resource(&pdev-dev, res);if (IS_ERR(pwm-base)return PTR_ERR(pwm-b

25、ase);pwm-clk = devm_clk_get(&pdev-dev, NULL);if (IS_ERR(pwm-clk)return PTR_ERR(pwm-clk);pwm-data = match-data;pwm-chip.dev = &pdev-dev;pwm-chip.ops = &hisi_pwm_ops;pwm-chip.base = -1;pwm-chip.npwm = pwm-data-npwm;pwm-chip.can_sleep = true;/pwm-chip.of_xlate = of_pwm_xlate_with_flags;/pwm-chip.of_pwm

26、_n_cells = 3;spin_lock_init(&pwm-ctrl_lock);ret = pwmchip_add(&pwm-chip);if (ret dev, failed to add PWM chip: %dn, ret); return ret;platform_set_drvdata(pdev, pwm);return 0;/clk_error:/ pwmchip_remove(&pwm-chip);/ return ret;)static int hisi_pwm_remove(struct platform_device *pdev)(struct hisi_pwm_c

27、hip *pwm = p I a tf o r m_g et_d rvd a ta (p d e v);return pwmchip_remove(&pwm-chip);static struct platform_driver hisi_pwm_driver = .driver = .name = hisi-pwm,.of_match_table = hisi_pwm_of_match,).,probe = hisi_pwm_probe,.remove = hisi_pwm_remove,);module_platform_driver(hisLpwm_driver);/ 宏展开为驱动入口M

28、ODULE_ALIAS(platform:hisi-pwm);MODULE_AUTHOR(zjh );MODULE_DESCRIPTION(zd hisi3559a PWM driver);MODULE_LICENSE(GPL v2);4.时钟驱动修改在hi3559avl00-clock.h最后增加如下定义/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/ add by zjh/

29、add by zjh/ add by zjh/ add by zjh/ add by zjh#define HI3559AV100_SHUB_PWM2_CLK#define HI3559AV100_SHUB_PWM3_CLK#define HI3559AV100_SHUB_PWM6_CLK#define HI3559AV100_SHUB_PWM7_CLK修改clk-hi3559avl00.c文件内容add by zjh为修改内容/* shub div elk */struct clk_div_table shub_spi_clk_table = 0, 8,1, 4,2, 2;struct cl

30、k_div_table shub_spi4_clk_table = 0, 8,1, 4,2, 2,3, 1;struct clk_div_table shub_uart_div_clk_tableQ = 1, 8,2, 4;struct clk_div_table shub_pwm_clk_table = 0, 64,1, 8,2, 4,3, 2,4, l;/add by zjh struct hisi_divider_clock hi3559avl00_shub_div_clks _initdata = HI3559AV100_SHUB_SPI_SOURCE_CLK, clk_spi_clk

31、, shub_clk, 0, 0 x20, 24, 2, CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table, HI3559AV100 SHUB UART DIV CLK, elk uart div elk, shub elk, 0, Oxlc, 28, 2, CLK DIVIDER ALLOW ZERO, shub uart div elk table, HI3559AV100_SHUB_PWM_SOURCE_CLK, clk_pwm_clk, shub_clk, 0, 0 x18, 8, 3, CLK_DIVIDER_ALLOW_ZERO, shub_pw

32、m_clk_table,/ add by zjh );/* shub gate elk */static struct hisi_gate_clock hi3559avl00_shub_gate_clks _initdata = HI3559AV100_SHUB_SPI0_CLK , clk_shub_spiO, clk_spLclk,0, 0 x20, 1, 0, HI3559AV100_SHUB_SPIl_CLK , clk_shub_spil, clk-SpLcIk,0, 0 x20, 5, 0, HI3559AV100_SHUB_SPI2_CLK , clk_shub_spi2, clk_spLclk,0, 0 x20, 9, 0,shu b_u a rt_so u rce_clk, shub_uart_source_clk, shu b_u a rt_source_clk, shu b_u a rt_so u rce_clk, shub_uart_sour