《精通VerilogHDL：IC设计核心技术实例详解》书后习题以及答案

1、 实例程序第 1 章 习题 、 及 。0.3pfTr=0.02图 1-65 电路操作情形举例第 2 章 习题 。 8 321000000100100001100module ex2_2;/test benchreg clk=0;reg 7:0in=0;always #10 clk=clk;reg 1:0 sel=0;always(posedge clk)sel=sel+1;integer seed=4;always(posedge clk)in=$random(seed);/Circuitwire 7:0 out0=(sel=0)?in:0;wire 7:0 out1=(sel=1)?in:0

2、;wire 7:0 out2=(sel=2)?in:0;wire 7:0 out3=(sel=3)?in:0;endmodule3 6 3 module ex2_3;/test benchreg clk=0;reg 2:0in=0;always #10 clk=clk;integer seed=4;always(posedge clk)in=$random(seed);wire 5:0 out=(in=0)?0:(in=1)?1:(in=2)?4:(in=3)?9:(in=4)?16:(in=5)?25:(in=6)?36:(in=7)?49:0;endmodule always(posedg

3、e clk or negedge nrst)db=0;always(posedge clk or negedge nrst)if (nrst)beginor_reg=0; add_reg=0;xor_reg=xor_op; and_reg=and_op;or_reg=or_op;add_reg=add_op;endreg 3:0 da,db,xor_reg,and_reg,or_reg,add_reg;always(posedge clk or negedge nrst)if (nrst) beginda=0;db=0;end else beginda=din_a;db=din_b;endwi

4、re 3:0 xor_op=da db;wire 3:0 and_op=da & db;wire 3:0 or_op=da | db;wire 3:0 add_op=da + db;always(posedge clk or negedge nrst)if (nrst) beginxor_reg=0; and_reg=0;or_reg=0; add_reg=0;end else beginxor_reg=xor_op; and_reg=and_op;or_reg=or_op; add_reg=add_op;end由+ A3B3doutDQA1B1图 2-42 电路示例wire 3:0 A,B;

5、wire temp3=(A3B3);wire temp2=( A2&B2);wire temp1=( A1&B1);wire temp0=( A0|B0);wire tmp=temp3 | temp2 | temp1 | temp0;always(posedge clk) dout= tmp; module ex2_6;/test benchreg clk=0,nrst=1,sel=0;reg 7:0 din=0,dout;always #10 clk=clk;initial begin#50 nrst=0;#70 nrst=1;#80 sel=1;#15 sel=0;endinteger s

6、eed=4;always(posedge clk)din=#1 $random(seed);/circuitwire 7:0 temp=dout1:0,dout7:2;always (posedge clk or negedge nrst)if (nrst)dout=0;else if (sel=1) dout=din;elsedout=temp;endmodule8 308wire 7:0 in;wire 2:0 out= (in=0)? 3b000:(in=1)? 3b001:(in=2)? 3b010:(in=3)? 3b011:(in=4)? 3b100:(in=5)? 3b101:(

7、in=5)? 3b101:(in=6)? 3b110:(in=7)? 3b111:0;9 4 。reg 3:0 cntr;wire jump2=(cntr=0) | (cntr=5) | (cntr=7) ;always(posedge clk or negedge nrst)if (nrst)else if (jump2)elsecntr=0;cntr=cntr+2;cntr=cntr+1;的第 3 章 习题reg clk=0;initial forever #10 clk=clk;在本章中提到的循环语句有的always(posedge clk or negedge nrst)if (nrs

8、t)q=0;elseq=d;always(posedge clk)if (nrst)q=0;elseq=d; 的 的 。0dddDQDQdclknrstnrstclkalways(posedge clk)beginB=A;A=C;endbeginB=A;A=C;end | | | |xor_op=(A7A6)| (A5A4)| (A3A2)| (A1A0);endfunctionalways(A or B or C or D)beginY1=A & B | xor_op(C);Y2=Y1 & D;end第 4 章 习题图 4-39 状态变化图parameter state0=2b00,stat

9、e1=2b01,state2=2b10;reg 1:0 nxt_state,current_state;reg y;always(posedge clk or negedge nrst)if (nrst) current_state=state0;else current_state=nxt_state;always(current_state or x)case(current_state)state0: beginif (x=0) beginy=0;nxt_state=state0;end else if (x=1) beginy=1;nxt_state=state1;endendstat

10、e1: beginif (x=0) beginy=1;nxt_state=state1;end else if (x=1) beginy=0;nxt_state=state2;endendstate2: beginif (x=0) beginy=1;nxt_state=state0;endenddefault: beginy=0;nxt_state=state0;endendcase8module graycntr (gray, clk, inc, rst_n);parameter SIZE = 4;output SIZE-1:0 gray;input clk, inc, rst_n;reg SIZE-1:0 gnext, gray, bnext, bin;integer i;always (posedge clk or negedge rst_n)if (!rst_n) gray = 0;else gray = gnext;always (gray or inc) beginfor (i=0; ii);bnext = bin + inc;gnext = (bnext1) bnext;endendmodule第 5 章 习题 于CS 为个有个 直接读取个为write cycleread cycle图 5-29 时序图第 6 章 习题4 见 8 8 见 解4位