讲义文稿hspice教程

1、AgendaIntroduction1Verilog-A Modules2DAY1Synopsys 60-I-032-BSG-005 2007 Synopsys, Inc. All Rights ReservedSimulating Variability Design forYield3Unit ObjectivesAfter completing this unit, you should be able to:Use Verilog-A modules2Unit ObjectivesThis is an Instructor Guide page!Switch to Notes view

2、.Introduction to Verilog-AWhat is Verilog-AStandard analog hardware description language The analog-only subset of Verilog-AMSVerilog-AMS LRM, version 2.2, released in November 2004Verilog-A applicationsMulti-level design simulationCompact modelsAnalog test benchesVerilog-A in HSPICECompiled Verilog

3、-A SolutionSingle kernel simulation3Introduction to Verilog-AThis is an Instructor Guide page!Switch to Notes view.Feature Overview (1/2)Production since W-2005.03Compiled-code SolutionHigh performance with golden accuracySupports up-to-date Verilog-A language featuresCompatible with Verilog-AMS LRM

4、 2.2Provides industry standard compliant Verilog-A language support Users can use existing Verilog-A code without any changesProvides HSPICE Verilog-A device support with existing syntaxVerilog-A modules are instantiated in the same manner as HSPICE subcircuitsAll major features available on HSPICE

5、will be supported in Verilog-A based devicesUsers do not lose any significant simulator functionality when simulating with Verilog-A based devices4Feature Overview (1/2)This is an Instructor Guide page!Switch to Notes view.Feature Overview (2/2)All major analysis types available on HSPICE are suppor

6、ted in Verilog-A based devices DC analysisAC analysis (.AC, .LIN, .NET)Transient analysis (.TRAN, .FFT, .FOUR) Noise analysisPole-Zero analysisSweeping, Monte Carlo, OptimizationAlter analysis5Feature Overview (2/2)This is an Instructor Guide page!Switch to Notes view.Verilog-A Usage Overview Verilo

7、g-A modules are loaded into the system via “.hdl” commandModules are instantiated with the same syntax as HSPICE subcircuitsVerilog-A device data can be output using conventional output commands* Simple Verilog-A amplifier.hdl my_amp.vavs 1 0 1rs 1 0 1x1 1 2 my_amp gain=10rl 2 0 1.print tran V(x1.in

8、) I(x1.out) x1:gainmodule my_amp(in, out);electrical in, out;parameter real gain = 1.0; analog begin V(out) + gain * V(in); endendmodule6Verilog-A Usage Overview This is an Instructor Guide page!Switch to Notes view.Loading Verilog-A Files (1/2) Two ways to load Verilog-A files.hdl netlist commandFo

9、llows the syntax of NanoSimExamples:.hdl “my_amp.va”.hdl “va_res” $ searching for va_res.va file-hdl command line optionAllows simulations to choose whether Verilog-A modules are used or notVerilog-A modules can be changed without netlist modificationEach Verilog-A file used needs one hdl optionExam

10、ples:hspice test.sp hdl pll.va vamodel o testhspice input.sp hdl my_amp.va o va_testhspice pll.sp hdl chrgp hdl vco o pll_test A Verilog-A file is assumed to have the .va extension when only prefix is supplied7Loading Verilog-A Files (1/2) This is an Instructor Guide page!Switch to Notes view.Loadin

11、g Verilog-A Files (2/2)The .hdl command may be placed anywhere in the top-level circuitCan be placed in .alter blocksCannot be inside subcircuit definitionCannot be inside if-else statementThe -hdl is the command line equivalent to the netlist .hdl command-hdl has higher priority than .hdl netlist c

12、ommandIf a Verilog-A module has the same name as a previously loaded module, or the names differ in case only, the later one will be ignored If a Verilog-A module has name conflict with any HSPICE built-in model name, the Verilog-A definition will be ignoredBuilt-in model name:R, C, D, L, N/PMOS, NP

13、N, PNP, etc.8Loading Verilog-A Files (2/2)This is an Instructor Guide page!Switch to Notes view.Defining the Verilog-A Module PathTwo methods to define the Verilog-A module search path-hdlpath command line option Example:hspice amp.sp hdlpath /vamodules hdl amp.vaHSP_HDL_PATH environment variableExa

14、mple:setenv HSP_HDL_PATH /shared_libs/verilogaThe directory search order for Verilog-A filesCurrent working directoryPath defined by hdlpathPath defined by HSP_HDL_PATH9Defining the Verilog-A Module PathThis is an Instructor Guide page!Switch to Notes view.Instantiation SyntaxVerilog-A devices are X

15、 devices in HSPICE netlistSyntaxX * moduleName|modelName *Verilog-A devices may have zero or more nodes and, zero or more parametersExample:Xva_r plus minus va_r res=100Verilog-A module may be instantiated directly or instantiated via an associated Verilog-A model cardDefault HSPICE search order for

16、 cell definition for X devicesSubcircuit Definition Verilog-A Model CardsVerilog-A Module Definition10Instantiation SyntaxThis is an Instructor Guide page!Switch to Notes view.Verilog-A Model Cards Model card is a parameter sharing mechanismWhen parameter sets are almost the same they can be shared

17、among many instancesAdvantage to compact modelSyntax is the same for Verilog-A devices as for built-in devicesVerilog-A model syntax.model modelName modelType param=valuemodelType - Verilog-A module name, cannot conflict with built-in model types (e.g., R, C, D, etc.)modelName - model name reference

18、 used by the instance Example:.model my_bjt_va bjt_va rb=6.5 rc=6.3 re=0.15 11Verilog-A Model Cards This is an Instructor Guide page!Switch to Notes view.Instantiation Examples (1/2)/ Verilog-A module examplemodule va_amp(in, out);electrical in,out;parameter real gain=1.0, fc=100e6;analog beginendmo

19、duleOne Verilog-A module can have one or more optional associated model cardsExamples:.model myamp_model va_amp gain=2 fc=200e6.model myamp_model_2 va_amp gain=10Any module parameter can be specified on its model cards or on the instance Instance parameters override model parameters 12Instantiation

20、Examples (1/2)This is an Instructor Guide page!Switch to Notes view.Instantiation Examples (2/2)Instantiations of Verilog-A module va_amp x1 n1 n2 myamp x2 n3 n4 myamp gain=2.0 x3 n5 n6 myamp2 fc=150e6 x4 n7 n8 va_amp x1 inherits model myamp parameters gain=2, fc=200e6x2 inherits fc=200e6 from myamp

21、 and overrides gain x3 inherits parameter “gain=10” from model myamp2 and overrides parameter fc which is an implicit parameter in myamp2x4 directly instantiates the Verilog-A module va_amp 13Instantiation Examples (2/2)This is an Instructor Guide page!Switch to Notes view.Parameter Case Sensitivity

22、Verilog-A is case sensitiveHSPICE is case insensitiveModule parameters that differ by case only cannot be redefined in its netlist instantiations Example:module my_amp(in, out);electrical in, out;parameter real gain = 1.0;parameter real Gain = 1.0;analog V(out) in4 are mapped to ports in1 - in4Make

23、sure that the instantiation order matches the vector port order defined in the module15Bus SupportThis is an Instructor Guide page!Switch to Notes view.Output Control (1/2)Output for Verilog-A devices:Direct port voltage accessDirect port current probingInternal node voltage accessInternal named bra

24、nch probingModule parameter valueModule variable valueV() and I() access functionsPort voltage and internal node voltages are accessed via the V() functionInternal node access requires the full hierarchical namePort current and named branch currents are accessed via the I() function16Output Control

25、(1/2)This is an Instructor Guide page!Switch to Notes view.Output Control (2/2)Reporting Convention for CurrentsA positive branch current implies that current is flowing into the device terminal or internal branchModule Parameter Output SyntaxInstance_name:parameterExample:.print xva_r:reffplusminus

26、Xva_rI(xva_1:plus)I(xva_1:minus)17Output Control (2/2)This is an Instructor Guide page!Switch to Notes view.Output Control Example (1/2)Verilog Module/ Verilog-A modulemodule va_fnc(plus, minus);electrical plus, minus;electrical int1, int2;parameter real r1=0, r2=0;branch (int1, int2) br1;/ creates

27、an internal branch br1 between/ internal nodes int1 and int2;child_module c1 (plus, int1);child_module c2 (minus, int2);EndmoduleVerilog-A device in netlistx1 1 2 va_fnc r1=1 r2=218Output Control Example (1/2)This is an Instructor Guide page!Switch to Notes view.Output Control Example (2/2)To print

28、the current on Verilog-A device port name plus for the instance x1:.print I(x1.plus)To print the Verilog-A module internal node named int1 for the instance x1: .print V(1)In this module there is an internal branch name br1 declared then, the branch current can be probed as:.print I(x1.br1)If t

29、he module va_fnc is hierarchical and has a child instance called c1 with an internal node c_int1 then the node c_int1 can be output as:.print V(x1.c1.c_int1)Wildcarding can be use to output internal nodes, int1 and int2 for the child c1 in the instance x1:.print v(*)19Output Control Example

30、 (2/2) This is an Instructor Guide page!Switch to Notes view.Overriding Subcircuits with Verilog-A ModulesIf both a subcircuit and a Verilog-A module have the same case-insensitive name, by default, HSPICE uses the subcircuit definitionVamodel option lets Verilog-A definition take preferenceSupports

31、 cell-base definition onlyCan be specified as a netlist option or a command line optionNetlist option syntax:.option vamodel =nameExamples:.option vamodel=vco vamodel=chrgpumpInstances of vco and chrgpump will use Verilog-A definition .option vamodelAll cell instantiations will use Verilog-A definit

32、ion whenever it is availableCommand line option: vamodelhspice input.sp hdl va_models vamodel chrgpump vamodel vco20Overriding Subcircuits with Verilog-A ModulesThis is an Instructor Guide page!Switch to Notes view.Disabling .option VAMODEL with .option SPMODEL.option spmodel switches back to HSPICE

33、 definitionSupports cell-based definitions onlyUseful for .ALTER blocksNetlist Syntax.option spmodel =nameExamples:Specific module.option spmodel=vcoAssuming switched to a Verilog-A module in an earlier .alter blockInstantiations of vco will use subckt definition againGlobal .option spmodelAll cell

34、instantiations will use subckt definitionsThere is no equivalent command line option for spmodel21Disabling .option VAMODEL with .option SPMODELThis is an Instructor Guide page!Switch to Notes view.Addition Information vamodel and spmodelCommand line option -vamodel has preference over any netlist v

35、amodel or spmodel optionsExample:hspice va_opt.sp hdl va_models vamodel my_capEvery run uses the Verilog-A definition for cell my_capSpecific vamodel and spmodel options have preference over global optionsExamples:* va_opt.spi* all will use Verilog-A definition whenever available.option vamodel.alter 1* a