讲义参考ni培训6.labview fpga algorithm design-digital protocol case study

1、LabVIEW FPGA Algorithm Design Digital Protocol Case StudyFPGA Design FlowState MachinesReset BehaviorsSimulation and Debug in LabVIEWLabVIEW FPGA Algorithm Design Digital Protocol Case StudyState Machine TheoryStates represent logical configurations of the memory of a systemTransitions occur when ce

2、rtain input conditions are met, and can initiate actions and/or update outputs when entering or exiting a stateState A: Entry ActionState B: Entry ActionExit ActionTransition ConditionState Machine TheoryTransition Conditions are based on inputsEntry and Exit Actions update outputs, and are based on

3、 inputs and current stateState A: Entry ActionState B: Entry ActionExit ActionTransition ConditionState Machine ExampleYou are either programming or waiting on a compile to finish. When programming, your boss may tell you to hurry, at which point you press compile to initiate a compilation. After th

4、e computer is done compiling, it notifies you by indicating that it is done.Waiting: compile, done = FALSEProgramming:hurry = FALSEcompile = TRUEhurry = TRUEdone = TRUEState Machines in LabVIEWState-Specific Output LogicState-Specific Next State LogicGeneric Next State LogicGeneric Output LogicAddit

5、ional “State”Additional “State”State Machine TimingDecision and/or I/O rate = loop rate, by defaultMay want to dynamically support multiple rates, decouple decision-making and I/O rates, etc.Must conditionally execute state machine, introduce additional states, or modify action timing to “slow” exec

6、utionState-Specific Output LogicState-Specific Next State LogicGeneric Next State LogicGeneric Output LogicInputs sampled, next state selected, and outputs calculated each clock cycle/loop iterationState Machine TimingOption 1: Conditionally execute state machineOption 2: Wait state for every stateO

7、ption 3: One wait state, but must calculate subsequent transition in advanceOption 4: Wait in-state, but use entry and output actionsState Machine TimingOption 1: Conditionally execute state machineState-Specific Output LogicState-Specific Next State LogicGeneric Next State LogicGeneric Output Logic

8、State A: Entry ActionState C: Entry ActionExit ActionC A transitionState B: Entry ActionA B transitionB C transitionExit ActionExit ActionState Machine TimingOption 1: Conditionally execute state machineState A: Entry ActionState C: Entry ActionState B: Entry ActionState Machine TimingOption 1: Cond

9、itionally execute state machineClocking OptionsDivide by NSimpleLimited resolution and no operation close to loop rateState Machine TimingDirect Digital Synthesis (DDS)Fractional accumulator more complexHigh resolution and operation up to loop rateLogic clocked by state machine must be able to execu

10、te within minimum periodFor example: To execute at 26.6% of the loop rate (loop rate / 3.75), 75% of the time the code will execute every 4 loop iterations, and 25% of the time the code will execute every 3 loop iterations, so signals connected to state machine output must tolerate minimum (3 / loop

11、 rate) period.State Machine TimingOption 2: Wait state for every stateState A: Entry ActionState C: Entry ActionState B: Entry ActionWait AWait BWait CState Machine TimingOption 3: Single wait stateState A: Entry ActionState C: Entry ActionState B: Entry ActionWaitNext State = CNext State = ANext St

12、ate = BState Machine TimingOption 4: Wait in-stateState A: Entry ActionState C: Entry ActionState B: Entry ActionWaiting doneWaiting doneWaiting doneWaitingWaitingWaitingState Machine TimingComparing OptionsProsConsOption 1: Conditionally execute state machine Simple to implement in LabVIEW Easy to

13、support DDS-based rates Increased critical path length All code must execute at divided rateOption 2: Wait state for every state Minimal logic for highest loop frequencies State diagram complexity Increases width of state encoding (could enter critical path) Must execute wait state at least onceOpti

14、on 3: Single wait state Adds only one state Must reproduce much of the transition logic in wait state, or decide upon the following state (after wait) in prior state, adding latency Must execute wait state at least onceOption 4: Wait in-state Minimizes number of states Execution can occur at loop ra

15、te Adds some complexity to each state (calculate outputs upon first execution of state vs. each execution)Case Study: About SPISerial Peripheral InterfaceMaster/Slave architectureBi-directional, full-duplexMSB-firstClock must be gated by MasterActive low Slave SelectCPHA determines whether inputs la

16、tched on 1st or 2nd clock edgeCPOL determines polarity of clockSource: WikipediaCase Study: SPI ImplementationTo ensure explicit clock level, use digital output rather than clock output pin100 MHz target loop rate for 50 MHz SPI interface speedChoose Option 4, wait in-state representationUp to 32 bi

17、t data wordsData to write must be MSB-packedData read is LSB-packedTX control (toggled by host) latches data word and word length, initiates transferFPGA Design FlowDesign behavioral modelEstablish functional requirementsEstablish performance requirementsThroughput / SpeedPrecisionIncorporate target

18、 knowledge Use processor-optimized functions and toolkitsImplement structural IP on FPGARe-useLabVIEW built-inXilinx CORE GeneratorIPNet/NI LabsCreateLabVIEWConvert to FXPSchedule codeInside SCTLOutside SCTLVHDLSimulationFunctional simulation under My ComputerSimulated or previously-obtained dataCat

19、ches implementation errors before compilationCompileStart with target clock rateAnalyze timing margins and critical pathTestSimulated data at speedReal-world I/ODoes not meet timing or size requirementsCannot realize behavioral modelSimulation does not function correctly or meet performance requirem

20、entsDesign does not meet performance requirements in real-world operating conditionsFPGA Design FlowImplement structural IP on FPGARe-useLabVIEW built-inXilinx CORE GeneratorIPNet/NI LabsCreateLabVIEWConvert to FXPSchedule codeInside SCTLOutside SCTLVHDLSimulationFunctional simulation under My Compu

21、terSimulated or previously-obtained dataCatches implementation errors before compilationCompileStart with target clock rateAnalyze timing margins and critical pathTestSimulated data at speedReal-world I/ODoes not meet timing or size requirementsCannot realize behavioral modelSimulation does not func

22、tion correctly or meet performance requirementsDesign does not meet performance requirements in real-world operating conditionsDesign behavioral modelEstablish functional requirementsEstablish performance requirementsThroughput / SpeedPrecisionIncorporate target knowledge Use processor-optimized fun

23、ctions and toolkitsCase Study: Master SPI EngineLatch MISO and Toggle SCLKWait for TXAssert MOSI and Toggle SCLKRESETAssert MOSIToggle SCLKCPHA = 0CPHA = 1_SS = 0_SS = 1_SS = 1_SS = 0CCount HCPCCount HCPCCount HCPCCount HCPDCount = 0 & CPHA = 1- HCP Half Clock Period- CCount = HCP assumed for some t

24、ransitions- All cases have path to RESETDCount != 0DCount = 0 & CPHA = 0FPGA Design FlowSimulationFunctional simulation under My ComputerSimulated or previously-obtained dataCatches implementation errors before compilationCompileStart with target clock rateAnalyze timing margins and critical pathTes

25、tSimulated data at speedReal-world I/ODesign behavioral modelEstablish functional requirementsEstablish performance requirementsThroughput / SpeedPrecisionIncorporate target knowledge Use processor-optimized functions and toolkitsDoes not meet timing or size requirementsCannot realize behavioral mod

26、elSimulation does not function correctly or meet performance requirementsDesign does not meet performance requirements in real-world operating conditionsImplement structural IP on FPGARe-useLabVIEW built-inXilinx CORE GeneratorIPNet/NI LabsCreateLabVIEWConvert to FXPSchedule codeInside SCTLOutside S

27、CTLVHDLCase Study: Master SPI EngineLatch MISO and Toggle SCLKWait for TXAssert MOSI and Toggle SCLKRESETAssert MOSIToggle SCLKCPHA = 0CPHA = 1_SS = 0_SS = 1_SS = 1_SS = 0CCount HCPCCount HCPCCount HCPCCount HCPDCount = 0 & CPHA = 1DCount != 0DCount = 0 & CPHA = 0FPGA Design FlowImplement structural

28、 IP on FPGARe-useLabVIEW built-inXilinx CORE GeneratorIPNet/NI LabsCreateLabVIEWConvert to FXPSchedule codeInside SCTLOutside SCTLVHDLCompileStart with target clock rateAnalyze timing margins and critical pathTestSimulated data at speedReal-world I/ODesign behavioral modelEstablish functional requir

29、ementsEstablish performance requirementsThroughput / SpeedPrecisionIncorporate target knowledge Use processor-optimized functions and toolkitsDoes not meet timing or size requirementsCannot realize behavioral modelSimulation does not function correctly or meet performance requirementsDesign does not

30、 meet performance requirements in real-world operating conditionsSimulationFunctional simulation under My ComputerSimulated or previously-obtained dataCatches implementation errors before compilationCase Study: SPIDigital Debugging: Instrument the FPGA CodeCase Study: SPIDigital Debugging: Host Code

31、Case Study: SPIDigital Debugging: Host CodeCase Study: SPIDigital Debugging: Debug DisplayCase Study: SPIDigital Debugging: Debug DisplayLatch MISO and Toggle SCLKWait for TXAssert MOSI and Toggle SCLKRESETAssert MOSIToggle SCLKCPHA = 0CPHA = 1_SS = 0_SS = 1_SS = 1_SS = 0CCount HCPCCount HCPCCount H

32、CPCCount HCPDCount = 0 & CPHA = 1DCount != 0DCount = 0 & CPHA = 0Case Study: SPIDigital Debugging: Debug DisplayLatch MISO and Toggle SCLKWait for TXAssert MOSI and Toggle SCLKRESETAssert MOSIToggle SCLKCPHA = 0CPHA = 1_SS = 0_SS = 1_SS = 1_SS = 0CCount HCPCCount HCPCCount HCPCCount HCPDCount = 0 &

33、CPHA = 1DCount != 0DCount = 0 & CPHA = 0CPHA = 1Case Study: SPIDigital Debugging: Debug DisplayCPHA = 1Case Study: SPIDigital Debugging: Debug DisplayCPHA = 1CPOL = 1Case Study: SPIDigital Debugging: Debug DisplayCPHA = 0CPOL = 0Data Length = 8 Case Study: SPIDigital Debugging: Debug DisplayCPHA = 0

34、CPOL = 0Data Length = 32 Case Study: SPIDigital Debugging: Debug DisplayCPHA = 0CPOL = 0Data Length = 32HCP = 2 Case Study: SPIDigital Debugging: Slave StimulusTwo options:Build structural model of slave on FPGAComplete coverageMore challenging implementationEmulate slave behavior with test bench an

35、d / or fixed test vectorSimpler implementationMay not “respond” to all master stimulusCase Study: SPIDigital Debugging: Slave Stimulus (FPGA)Case Study: SPIDigital Debugging: Slave Stimulus (Host)Case Study: SPIDigital Debugging: Slave Stimulus (Host)CPHA = 0CPOL = 0Case Study: SPIDigital Debugging:

36、 Slave Stimulus (Host)CPHA = 1CPOL = 0Case Study: SPIDigital Debugging: Slave Stimulus (Host)CPHA = 1CPOL = 1FPGA Design FlowImplement structural IP on FPGARe-useLabVIEW built-inXilinx CORE GeneratorIPNet/NI LabsCreateLabVIEWConvert to FXPSchedule codeInside SCTLOutside SCTLVHDLSimulationFunctional

37、simulation under My ComputerSimulated or previously-obtained dataCatches implementation errors before compilationTestSimulated data at speedReal-world I/ODesign behavioral modelEstablish functional requirementsEstablish performance requirementsThroughput / SpeedPrecisionIncorporate target knowledge

38、Use processor-optimized functions and toolkitsDoes not meet timing or size requirementsCannot realize behavioral modelSimulation does not function correctly or meet performance requirementsDesign does not meet performance requirements in real-world operating conditionsCompileStart with target clock

39、rateAnalyze timing margins and critical pathCase Study: SPICompilationFPGA Design FlowImplement structural IP on FPGACreateLabVIEWVHDLRe-useLabVIEW built-inXilinx CORE GeneratorSimulationOn the hostSimulated or previously-obtained dataCatches implementation errors before compilationCompileStart with

40、 target clock rate; vary to explore IP limitationsConcurrent compilations with compile serverDoes not meet timing or size requirementsCannot realize behavioral modelSimulation does not function correctly or meet performance requirementsDesign does not meet performance requirements in real-world oper

41、ating conditionsDesign behavioral modelUse host-based functions and toolkitsEstablish performance requirementsThroughput / SpeedFixed pointIncorporate target knowledgeTestSimulated data at speedReal-world I/OClock SamplingWhen receiving source-synchronous transmissions and clock only available on da

42、ta line (as opposed to regional or global clock input)Must sample (loop rate) as least 2x faster than maximum clock frequency, in accordance with NyquistSimilar implementation options as Master SPI caseState MachineSlave SPI EngineAssert MISOWait for _SSLatch MOSIRESET_SS = 0 & SCLK edge & CPHA = 1

43、| _SS falling edge & CPHA = 0- All cases have path to RESETSCLK edgeSCLK edgeDcount = 0Exercise 6-1: Build, integrate with Master, and debug Slave SPI engineImplement a digital protocol / LabVIEW FPGA state machineDebug interactions between Master and Slave before compilingDigital DebouncingGlitches

44、 can be disregarded with de-bouncing logicUseful for:Sampling physical switchesHardware insertion/removalPower up detection (power supply stability)Filtering significant noise in low-frequency signalsMetastability potentially an issue use synchronization registersUndesirableSimple Debouncing ImplementationLatch