数字设计计数器复习chenyu

1、Counter(计数器)(P710)The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A counter with m states is called a modulo-m counter or, sometimes, a divide-by-m cou

2、nter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation. 8.4.1 Ripple Counters（行波计数器） use T flip-flopQ* = QQQT考虑二进制计数顺序：只有当第 i-1 位由10时，第 i 位才翻转。CLKQQTQQTQQTQQTQ0Q1Q2Q3T flip-flop changes state (toggles) on every rising edge of its clock input. synchronous

3、counter同步二进制加法计数器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。EN QT Q 利用有使能端的 T 触发器实现：Q* = ENQ + ENQ = EN Q通过EN端进行控制，需要翻转时，使 EN = 1 ENi = Qi-1 Qi-2 Q1 Q0EN0 = ? 11、logic abstraction，get state table(diagram) 逻辑抽象，得到状态图（表）2、State AssignmentUse binary intege

4、r 000111 as the code of S0 S7 Count the clock signal, input can not be needed. Moore machineC-out signal is output variable.Design a 3 bits modulo-8 binary counterS0/0S1/0S3/0S4/0S2/0S5/0S7/1S6/00001111101010010100111003、construct transition/output table，get transition equation and output equation S

5、0/0S1/0S3/0S4/0S2/0S5/0S7/1S6/00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Q2 Q1 Q0Q2*Q1*Q0*CS0S1S2S3S4S5S6S70 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 00000000100011111010100101001110001Q1Q0Q2Q0* 00 01 11 101 0 0 11 0 0 13、construct transition/output table，get transition equation and output equationQ0* = Q

6、00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Q2 Q1 Q0Q2*Q1*Q0*C0 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0000000010 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 000000001Q2 Q1 Q0Q2*Q1*Q0*C01Q1Q0Q2Q1* 00 01 11 100 1 0 10 1 0 1Q0* = Q0Q1* = Q1Q0 + Q1Q03、construct transition/ou

7、tput table，get transition equation and output equation0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 000000001Q2 Q1 Q0Q2*Q1*Q0*CQ0* = Q0Output equation：C = Q3 Q2 Q1Q1* = Q1Q0 + Q1Q001Q1Q0Q2Q2* 00 01 11 100 0 1 01 1 0 1Q2* = Q2Q1Q0 + Q2Q1 + Q2Q03、construct transition/o

8、utput table，get transition equation and output equationQ0* = Q0Q1* = Q1Q0 + Q1Q0Q2* = Q2Q1Q0 + Q2Q1 + Q2Q04、choose a flip-flop，get excitation equation 翻转Q* = Q（T filp-flop）Q* = ENQ + ENQQ1* = Q1Q0 + Q1Q0= Q2Q1Q0 + Q2 (Q1+Q0)= Q2Q1Q0 + Q2 (Q1Q0)EN1 = Q0EN2 = Q1Q0EN0 = 1Choose T flip-flop with enable5

9、、draw logic diagramEN0 = 1EN1 = Q0EN2 = Q1Q0C = Q3 Q2 Q11CLKQ0Q1Q2CQ* = ENQ + ENQChoose T flip-flop with enableQ0* = Q0Q1* = Q1Q0 + Q1Q0Q2* = Q2Q1Q0 + Q2Q1 + Q2Q08.4.3 MSI Counters and Applications4位二进制计数器74x16374x163的功能表01111CLK工作状态同步清零同步置数保持保持,RCO=0计数CLR_LLD_LENP ENT0111 0 1 0 1 174x161异步清零Connect

10、ions for the 74X163 to operate in a free-running mode(P715)74x163工作于自由运行模式时的接线方法Other MSI counters1bit BCD counter 74x160 Synchronous clear 、74x162 Asynchronous clear 01234567890QAQBQCQDOther MSI counters74x169-up/down counterUP/DNUP/DN = 1 counts up （升序）UP/DN = 0 counts down（降序）Enable inputsripple

11、carry outActive-lowABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATA如何控制地址端自动轮流选择输出Y0Y7 application of the counterTiming diagram for a modulo-8 binary counter and decoder,showing decoding glitches. 若在一次状态转移中有2位或多位计数位同时变化，译码器输出端可能会产生“尖峰脉冲” 功能性冒险01234567012电路?using the 163 as a mod

12、ulo-11 counter(用4位二进制计数器74x163实现模11计数器) 清零法S0S1S2S3S4S12S11S10S9S8S7S6S5S13S14S15计数到1010时，利用同步清零端强制为0000。 m2n 清零法计数到1010时，利用同步清零端强制为0000。 m2n 情况using the 163 as a modulo-11 counterCLKQ0Q1Q2Q3思考：如果是74x161（异步清零）可以这样连接吗？ 利用1011状态异步清零，会出现“毛刺”using the 163 as a modulo-11 counter 置数法 m2n 情况S0S1S2S3S4S12S1

13、1S10S9S8S7S6S5S13S14S15计数到1111时，利用同步预置数端强制输出为0101using the 163 as a modulo-11 counter 置数法 m 2n）先进行级联，再整体置零或预置数例：用74x163构造模193计数器 两片163级联得8位二进制计数器（0255） 采用整体清零法，0192 采用整体预置数法，63255 25619363 若 m 可以分解：m = m1m2 分别实现m1和m2，再级联6310 = ( 0011 1111 )2 CLKCLRLDENPENTA QAB QBC QCD QD RCO74x163 CLKCLRLDENPENTA Q

14、AB QBC QCD QD RCO74x16311001111+5VCLOCKCLR_L CLKCLRLDENPENTA QAB QBC QCD QD RCO74x163 CLKCLRLDENPENTA QAB QBC QCD QD RCO74x16311001111CLOCKCLR_L+5VQ4Q5Q6Q7ENWhat is the modulo of the circuit below? CLKCLRLDENPENTA QAB QBC QCD QD RCO74x163011+5VCLOCKQD QC QB QA0 0 0 00 1 1 00 1 1 11 0 0 01 1 1 01 1 1

15、 1 CLKCLRLDENPENTA QAB QBC QCD QD RCO74x16301+5VCLOCKModulo 12 counterQD：12分频占空比50What is the modulo of the circuit below?exerciseexerciseV. Analyze the circuit as shown below, which contains a 74x163 4-bit binary counter, a 74x138 decoder and a 74x153 4-input,1-bit multiplexer. When control input MN=10 for 74x153 multiplexer,151. Write out the logic expression of 74x153 output F. 52. Write out the sequence of states for the 74x161 in the circuit. 73. Describe the modulus(模) of the circuit. 3exerciseIV. Analyze the sequential-circuit as sho