案例eetop的dc总结帖digital system

1、ECE 551Digital System Design & SynthesisSynthesis:Constraint OptimizationsDesign Optimizations2Administrative MattersClass project posted later today at: Design of an Elliptic Curve Cryptography ProcessorSelection of Project Team Members Due Thursday, March 30Initial Report and Verilog - Due Tuesday

2、, April 18 (By 1:00 PM)Final Report and Verilog - Due Tuesday, May 2 (By 1:00 PM)Project Presentations May 2nd and 4thProject Demonstrations May 3rd and 4thDiscussed next Tuesday Todays discussion section 5:30pm-6:30pm in 3534 Engineering Hall File I/O, Tasks, Functions, Parameters, GenerateHomework

3、 #4 posted soonRelated to project can work in project teamsDue after Spring Break No class this Thursday (March 23rd) 3Constraint ExamplesMinimize Areamodule mac(input clk, rst, input 31:0 in, output 63:0 out);reg 31:0 constreg;reg 63:0 mult, add, result;reg 2:0 count;assign out = result;always (*)

4、mult = constreg * in;always (*) add = mult + result;always (posedge clk) begin if (rst) begin constreg = in; result = 0; count 0) begin result = add; count = count - 1; end else begin result = 0; count = 4; endendendmodule4Setting Design Constraintsset_max_area 20000Sets maximum area to 20,000 cell

5、unitsset_max_delay 4 -to all_outputs()Sets maximum delay of 4 to any outputset_max_dynamic_power 10mWSets maximum dynamic power to 10 mWcreate_clk “clk” period 10Specifies that port clk is a clock with a period of 10ns create_clk name “my_clk” period 12Creates a virtual clock called my_clk with a pe

6、riod of 12ns ; use with combinational logic5Constraint ExamplesCLK_PERIOD = 4 (250 MHz)MAX_AREA = 80000Arrival:3.73Slack:0.01Area:68122Slack = Clock_PERIOD Arrival Library Setup TimeLibrary Setup Time is typically about 0.25 ns for gflx-p6Constraint ExamplesCLK_PERIOD = 4MAX_AREA = 65000Arrival:3.75

7、Slack:0.00Area:647587Constraint ExamplesCLK_PERIOD = 4MAX_AREA = 60000Arrival:3.75Slack:0.00Area:633778Constraint ExamplesMaximize speedmodule mac(input clk, rst, input 31:0 in, output 63:0 out);reg 31:0 constreg;reg 63:0 mult, add, result;reg 2:0 count;assign out = result;always (*) mult = constreg

8、 * in;always (*) add = mult + result;always (posedge clk) begin if (rst) begin constreg = in; result = 0; count 0) begin result = add; count = count - 1; end else begin result = 0; count cmult_resources.rptLots of other report commands available26Design Optimization: FIR FilterUsed in signal process

9、ingPasses through some data but not all (filter!)Example: Remove noise from image/soundUses multipliers and addersMultiply constant “tap” value against time-delayed input valueIn the Verilog, y is out, bk is taps, and x is data27FIR Filter Design28Initial Design: Code 1module fir_init(clk, rst, in,

10、out); parameter bitwidth = 8; parameter ntaps = 4; parameter logntaps = 2; input clk, rst; input bitwidth-1:0 in; output reg bitwidth-1:0 out; reg bitwidth-1:0 taps 0:ntaps-1; reg bitwidth-1:0 data 0:ntaps-1; reg logntaps:0 count; integer i;29Initial Design: Code 2 always (posedge clk) begin if (rst

11、) begin / indicate we need to load all the tap values count = 0; / reset the data and taps for (i = 0; i ntaps; i = i + 1) begin: resetloop datai = 0; tapsi = 0; end end else if (count 0; i = i - 1) begin: loadtaps tapsi = tapsi-1; end / load the new value at tap0 taps0 = in; count 0; i = i - 1) beg

12、in: shiftdata datai = datai-1; end / load the new value at data0 data0 = in; end / else: !if(count ntaps) end / always (posedge clk) / compute the filtered result always (*) begin out = 0; for (i = 0; i ntaps; i = i + 1) begin: filterloop out = out + (datai * tapsntaps-1 - i); end endendmodule31Init

13、ial Design: SynthesisConstraintsCLK_PERIOD4INPUT_DELAY0.2OUTPUT_DELAY0.2MAX_AREA8000ResultsArrival Time3.13Slack.67 (MET)Area733532Initial Design: Schematic33Small Design: Code 1module fir_area(clk, rst, in, out); parameter bitwidth = 8; parameter ntaps = 4; parameter logntaps = 2; input clk, rst; i

14、nput bitwidth-1:0 in; output reg bitwidth-1:0 out; reg bitwidth-1:0 taps 0:ntaps-1; reg bitwidth-1:0 data 0:ntaps-1; reg bitwidth-1:0 partial; reg logntaps:0 count; reg logntaps-1:0 step; reg ready; integer i;34Small Design: Code 2 always (posedge clk) begin if (rst) begin / indicate we need to load

15、 all the tap values count = 0; ready = 0; / reset the data and taps for (i = 0; i ntaps; i = i + 1) begin: resetloop datai = 0; tapsi = 0; end end else if (count 0; i = i - 1) begin: loadtaps tapsi = tapsi-1; end / load the new value at tap0 taps0 = in; count = ntaps) begin ready = 1; count 0; i = i

16、 - 1) begin: shiftdata datai = datai-1; end / load the new value at data0 data0 = in; end / else: !if(count ntaps) end / always (posedge clk)36Small Design: Code 4/ compute the filtered result always (posedge clk) begin if (rst | ready) begin step = 0; partial = 0; end else begin if (step = 0) begin

17、 out = partial; partial = (data0 * tapsntaps-1); end else begin out = out; partial = partial + (datastep * tapsntaps-1 step); end if (step ntaps-1) step = step + 1; else step = 0; end endendmodule 37Small Design: SynthesisConstraintsCLK_PERIOD4INPUT_DELAY0.2OUTPUT_DELAY0.2MAX_AREA8000ResultsArrival

18、Time2.76 (vs. 3.13)Slack.92 (MET) (4 clock cycles)Area5754 (vs. 7335)38Small Design: Schematic39Fast Design: Code 1module fir_area(clk, rst, in, out); parameter bitwidth = 8; parameter ntaps = 4; parameter logntaps = 2; input clk, rst; input bitwidth-1:0 in; output bitwidth-1:0 out; reg bitwidth-1:0

19、 taps 0:ntaps-1; reg bitwidth-1:0 mult 0:ntaps-1; reg bitwidth-1:0 partial 0:ntaps-1; reg logntaps:0 count; integer i; assign out = partialntaps-1;40Fast Design: Code 2 always (posedge clk) begin if (rst) begin / indicate we need to load all the tap values count = 0; / reset the taps for (i = 0; i n

20、taps; i = i + 1) begin: resetloop tapsi = 0; end end else if (count 0; i = i - 1) begin: loadtaps tapsi = tapsi-1; end / load the new value at tap0 taps0 = in; count = count+1; end41Fast Design: Code 3 else begin / taps stay the same end / else: !if(count ntaps) end / always (posedge clk) / compute the filtered result (pipelined) always (posedge clk) begin / get the product of the input with each of the tap values for (i = 0; i ntaps; i = i + 1) multi = in * tapsi; / special case at front partial0 = mult0; / get th