数字逻辑设计及应用教学英文课件：Lec17-Chap 7

1、1Digital Logic Design and ApplicatonLecture #17Latches and Flip-FlopsUESTC, Spring 20132再谈串行输入加法器的实现Q DQ CXYCISiCi+1XiYiCiSCOCLK 暂存 X YCI COSCi+1SiXi YiCi时钟控制 电平有效还是边沿有效？串行输入、串行输出注意：时钟同步Iterative Vs. Sequential3Iterative Versus Sequential CircuitsC0C4X0 Y0X1 Y1X2 Y2X3 Y3S0S1S2S347.2 Latches and Flip

2、-FlopsLatcheschange its outputs at any time (enable input is asserted).Flip-Flopschange its outputs only when the clock changesCLKPositive-EdgeRising-EdgeNegative-dgeFalling-EdgeLevel triggeredEdge-triggered, ET57.2.5 Edge-Triggered D Flip-FlopsD QC QD QC QQQLDCLKmaster slaveQm When CLK=0, When CLK=

3、1, Qm follows D; Q is unchanging.Qm is unchanging, Q = Qm until the next rising CLK edge1. Master/Slave, Positive-edge-triggeredQ changes only when CLK rises from 0 to 16Timing Diagram for master-slave D F/FDCLKQQmD QC QD QC QQQLDCLKQmQ =D( )7DCLKQD Q CLK QLogic SymbolEdge-Triggered 8DCLKQDCLKQD Lat

4、ch D Flip-Flop edge-triggered when CLK is asserted对信号扰动不敏感受信号扰动影响9D flip-flop timing parametersPropagation delay ( from CLK )tpLH(CQ) tpHL(CQ) tsetup建立时间 thold 保持时间 Setup time ( D before CLK）Hold time ( D after CLK)D CLKQ在时钟上升边沿附近有一个时间窗口，在此窗口时间内，数据输入D不能改变，否则电路进入亚稳态。从输入信号D到来时刻至信号D达到稳定所持续的时间。从输入信号D达到稳

5、定至信号D被锁存器接受所持续的时间。102. Negative-Edge-Trigged D Flip-FlopD QC QD QC QQQNDCLKD Q CLK QD QC QD QC QQQLDCLKPositive-edge-triggered3. D Flip-Flop with preset and clear同步(synchronous)是指与时钟同步，即时钟触发条件满足时检测清零(置位)信号是否有效，有效则在下一个时间周期的触发条件下，执行清零(置位)；异步(asynchronous)是清零(置位)信号有效时，无视触发脉冲，立即清零(置位)。11123. D Flip-Flop

6、 with preset and clearCLKQQLDPR_LCLR_LPRD Q CLK QCLRasynchronous inputs behavior like the set and reset inputs on S-R latch. 100111110110013Timing Diagram for D flip-flop with preset and clearCLKPR_LCLR_LQL3. D Flip-Flop with preset and clearsynchronous inputs: PR(preset) and CLR(clear depend on the

7、 CLK14D Q CLK Q DinResetCLK?R有效，Q=0R无效，Q=Din DinReset_L?154. Commercial TTL D Flip-Flops (74LS74)P535Figure 7-20 PR_LCLR_LCLKDQQN维持阻塞结构Smaller and faster165. CMOS edge-triggered D circuitUses transmission gates in feedback loopsQDCLKDCLKTwo feedback loops (master and slave latches)Master Slave177.2.

8、6 D Flip-Flop with Enable2-inputMultiplexerD Q CLK QDENCLKQQLIf EN is asserted, the external D input is selected;if EN is negated, the current output is used. D QEN CLK QLogic Symbol 187.2.7 Scan Flip-FlopD Q CLK QDTECLKQQLTITE:Test EnableTI:Test inputTE=0, D is selected TE=1, TI is selectedD TETI C

9、LK QQ19TOTICLKTEWhen TE is negated, Q = DWhen TE is asserted, Q = TITOTICLKTE207.2.8 Master/Slave S-R Flip-FlopS QCR QCSRS QCR QQQNQmmasterslave21Master/Slave S-R Flip-Flop Timing Diagram暂时忽略延迟时间等动态特性 C unpredictableunpredictable22C Edge-Triggered?unpredictableunpredictableThe S-R flip-flop changes

10、its outputs only at the falling edge of C.But it is not truly edge triggered.Pulse-Triggered flip-flops237.2.8 Master/Slave S-R Flip-FlopSCRQQD QC QD QC QQQNDCLKS QCR QCSRQQNS QCR Qpostponed-output indicatorD Q CLK Qdynamic input indicator edge triggered247.2.9 Master/Slave J-K Flip-Flop消除主从S-R触发器存在

11、的约束条件利用反馈消除主从S-R触发器存在的约束条件 Q* = S + RQSR = 0 (constraints)S-R FFS QCR QCSRQQNS QCR QS = JQR = KQmeet SR=0JKCJ-K FF Characteristic EquationQ* = JQ + (KQ)Q(K+Q)QKQ J K Q 0 0 0 11 01 1 hold resetset toggleFunction Table 257.2.10 Edge-Triggered J-K Flip-FlopJ-K FF: Q* = JQ + KQD FF: Q* = D267.2.11 T Fli

12、p-FlopA T flip-flop changes state on every tick of the clock.QQTtoggleEN QT QT FF with EnableTQ27Design a T Flip-FlopUsing a D flip-flopD FF: Q* = DT FF: Q* = Q D = QUsing a J-K flip-flopJK: Q* = JQ + KQ T: Q* = Q J = K = 1TQQND Q CLK QTQQNJ QCLK K Q128T Flip-Flop with EnableT：Q* = ENQ + ENQ01EN Q Q

13、Q* Function Table JK：Q* = JQ + KQD：Q* = D297.2.11 T Flip-Flop 特征方程：Q* = Q QQT有使能端的T触发器： Q* = ENQ + ENQ EN QT Q说明： 传统中文教材中认为： T 触发器的特征方程 Q* = TQ + TQ T=1时翻转；T=0时维持 30关于电路结构和逻辑功能同一功能的触发器可用不同电路结构实现主从结构的D触发器、维持阻塞结构的D触发器同类电路结构可做成不同功能的触发器维持阻塞结构的：D触发器、J-K触发器电路构成的不同形式 下一状态Q* 与现态Q及输入之间在稳态下的逻辑关系31Summaries of Latch and Flip-FlopLatch: output chan