数字逻辑设计及应用教学课件：3-1数字电路中的电气知识

1、class-exercises1、Write the 8421 binary- coded decimal , Gray code,excess-3 representations for the decimal numbers: 5862、Indicate whether or not overflow occurs when adding the following 8-bit twos complement numbers: 1101 0100+ 1010 1011 0010 0110+ 0101 10101class-exercises1、Write the 8421 binary-

2、coded decimal ,excess-3 ,Gray code representations for the decimal numbers: 586.010110000110, 100010111001,11011011112、Indicate whether or not overflow occurs when adding the following 8-bit twos complement numbers: 1101 0100+ 1010 1011 0010 0110+ 0101 1010overflowoverflow2c h a p t e r 3 Digital Ci

3、rcuits数字电路electrical aspects of digital circuits数字电路中的电气知识3reviewPositive logic and nagitive-logic (正逻辑和负逻辑)Three basic logics：AND,OR, and NOTMethod:(方法)Truth table 真值表Logic expression 逻辑表达式Logic symbol 逻辑符号NAND and NOR (与非和或非)Timing diagram 定时图VOUTVINVccR获得高、低电平的基本原理43.2 Logic Families(逻辑系列) A logi

4、c family is a collection of different integrated-circuit chips that have similar input, output, and internal circuit characteristics, but that perform different logic functions . Chips from the same family can be interconnected to perform any desired logic function. On the other hand, chips from dif

5、fering families may not be compatible; they may use different power-supply voltages or may use different input and output conditions to represent logic values. 53.2 Logic Families (逻辑系列)(P85)1、transistor-transistor logic (TTL) （晶体管-晶体管逻辑）2、CMOS（互补MOS） MOS :metal-oxide semiconductor (金属-氧化物半导体) compl

6、ementary MOS (CMOS) 速度更高，功耗更低。63.3 CMOS Logic DC供电电压直流供电电压在逻辑图中被省略了，但它其实是连接在芯片的VCC引脚上的，而地则连接在GND 引脚上。电压和地在内部被分配给IC中的所有元素。73.3.1 CMOS Logic Levels CMOS逻辑电平 (P86)A typical CMOS logic circuit operates from a 5-volt power supply. 典型的CMOS逻辑电路在电源下工作！ （3.3V工作的CMOS称为低电压CMOS。）逻辑1（高）逻辑0（低）0.0V1.5V3.5V5.0V未定义逻

7、辑电平83.3.2 MOS Transistors (MOS晶体管)漏极 drain源极 source栅极 gateVgs+n沟道源极 source漏极 drain栅极 gate+Vgsp沟道Rds：压控电阻 Vgs(Vgs0) 增加，则Rds减少）Vgs(Vgs0)减少，则Rds减少9 3.3.3 Basic CMOS Inverter Circuit (P88)基本的CMOS反相器电路 常开开关： 当控制信号为高电平时，开关接通。（2） 常闭开关： 当控制信号为高电平时，开关断开。VoutVin=0Vin=1Vout10Inverter Circuit 倒相器结构Vin=0，Vout=1

8、in=0out常闭常开VccGND11Inverter Circuit 倒相器结构Vin=1，Vout=0in=1out常闭常开VccGND12VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter circuit (CMOS反相器)(P88)常闭常开常闭常开inP 沟道N沟道采用器件实现逻辑关系13VCCAZCMOS INVERTERVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gate2输入CMOS与非门(P90)Q214VCCAZCMOS INVERTERVDD = +5.0VZABCMOS 2-input NOR gate (CM

9、OS或非门)15VCCAZCMOS inverter VDD = +5.0VAZNoninverting Gate 非反相门(P93)取非再取非（CMOS缓冲器）16CMOS 2-INPUT AND GATE17使用与非门还是或非门？VDD = +5.0VZABCMOS NOR gateVDD = +5.0VZABQ4Q1Q3CMOS NAND gateQ218NAND VS. NOR(P92)CMOS NAND and NOR gates do not have identical performance. For a given silicon area, an n-channel tra

10、nsistor has lower “on” resistance than a p-channel transistor.Therefore, when transistors are put in series, k n-channel transistors have lower “on” resistance than do k p-channel ones. As a result, a k-input NAND gate is generally faster than and preferred over a k-input NOR gate.193.3.5 Fan-In(扇入)

11、(P92)The number of inputs that a gate can have in a particular logic family is called the logic familys fan-in. 20串联晶体管导通电阻的可加性 限制了MOS门的扇入数VDD = +5.0VZABVDD = +5.0VZAB the fan-in of CMOS gates, typically to 6 for NAND gates. the fan-in of CMOS gates, typically to 4 for NOR gates.21 The additive “on”

12、 resistance of series transistors limits the fan-in of CMOS gates, typically to 4 for NOR gates and 6 for NAND gates.The total delay through a 4-input NAND, a 2-input NOR, and an inverter is typically less than the delay ofa one-level 8-input NAND circuit.22 EXERCISE23ANSWER KEY FOR EXERCISEAND-OR-I

13、NVERT (coms AOI )gate243.4 Electrical Behavior of CMOS Circuits CMOS电路的电气特性(P96)Logic voltage levels. ( 逻辑电压电平)DC noise margins(直流噪声容限)Fanout.(扇出)Speed, Power consumption(速度、功耗)Noise, Electrostatic discharge(噪声、静电放电)Open-drain outputs. Three-state outputs (漏极开路输出、三态输出)253.5 CMOS Steady-State Electri

14、cal Behavior (P90)CMOS稳态电气特性263.5.1 Logic Levels and Noise Margins 逻辑电平和噪声容限VDD = +5.0VVOUTVINTpTn0 1 0127CMOS逻辑系列（HC）电平规格高态不正常状态低态VOLmaxVILmaxVIHminVOHminVCC0.1V地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc028直流噪声容限（DC noise margin）多大的噪声会使最坏输出电压被破坏得不可被输入端识别.高态不正常状态低态VOLmax=0.1VVILmax=1.35VVIHm