pwm控制直流电机_verilog_l9110

1、modulepwm(clk,en,speed,dir_in,pwm1,pwm2);inputclk;inputen;input2:0speed;inputdir_in;outputpwm1;outputpwm2;/regdir_out1;/regdir_out2;/regpwm_signal;wirew_dir1,w_dir2;counteru1(.clk(clk),.en_dir1(w_dir1),.en_dir2(w_dir2),.speed(speed),.out1(pwm1),.out2(pwm2);directionu2(.clk(clk),.dir_in(dir_in),.dir_

2、out1(w_dir1),.dir_out2(w_dir2);endmodulemodulecounter(clk,en_dir1,en_dir2,speed,out1,out2);inputclk;/系统时钟inputen_dir1;inputen_dir2;input2:0speed;/正转使能端/反转使能端/速度调节，3个档，100最快outputout1;outputout2;/输出正转/输出反转regout1;regout2;reg6:0cnt;/计数，用来产生波形always(posedgeclk)beginif(cnt7d100)cnt=cnt+7b1;elsecnt=7b0;e

3、ndalways(posedgeclk)beginif(en_dir1)if(speed=3b100)if(cnt7d10)out1=1b0;elseout1=1b1;elseif(speed=3b010)if(cnt7d80)/40)out1=1b0;else/3档，占空比90%/2档，占空比60%out1=1b1;elseif(speed!=3b000)/1档，占空比30%(实际上操作条件为“只要不等于000，就执行30%占空比”，挡位间能平滑过渡)if(cnt7d95)/70)out1=1b0;elseout1=1b1;elseout1=1b0;else/档位为0，输出0out1=1b0

4、;endalways(posedgeclk)beginif(en_dir2)if(speed=3b100)if(cnt7d10)out2=1b0;else/3档，占空比90%out2=1b1;elseif(speed=3b010)/2档，占空比20%if(cnt7d80)/40)out2=1b0;elseout2=1b1;elseif(speed!=3b000)/1档，占空比5%(实际上操作条件为“只要不等于000，就执行5%占空比”，挡位间能平滑过渡)if(cnt7d95)/70)out2=1b0;elseout2=1b1;elseout2=1b0;elseout2=1b0;endendmodule/档位为0，输出0moduledirection(clk,/方向控制模块，用来决定正转还是反转dir_in,dir_out1,dir_out2);inputclk;inputdir_in;outputdir_out1;/dir_out1=1，dir_out2=0时，正转；反之则反转outputdir_out2;regdir_out1;regdir_out2;always(posedgeclk)beginif(dir_in)/控制信号为1时，正转begindir_out1=1b1;d