闪速存储器M29F040英文数据手册

1、 Figure 1. Logic DiagramM29F0404 Mbit (512Kb x8, Uniform Block Single Supply Flash MemoryNOT FOR NEW DESIGNM29F040 is replaced by the M29F040B5V ± 10% SUPPLY VOLTAGE for PROGRAM,ERASE and READ OPERATIONSFAST ACCESS TIME: 70nsBYTE PROGRAMMING TIME: 10µs typicalERASE TIMEBlock: 1.0 sec typic

2、alChip: 2.5 sec typicalPROGRAM/ERASE CONTROLLER (P/E.C.Program Byte-by-ByteData Polling and Toggle bits Protocol forP/E.C. StatusMEMORY ERASE in BLOCKS8 Uniform Blocks of 64 KBytes eachBlock ProtectionMultiblock EraseERASE SUSPEND and RESUME MODESLOW POWER CONSUMPTIONRead mode: 8mA typical (at 12MHz

3、Stand-by mode: 25µA typicalAutomatic Stand-by mode100,000 PROGRAM/ERASE CYCLES perBLOCK20 YEARS DATA RETENTIONDefectivity below 1ppm/yearELECTRONIC SIGNATUREManufacturer Code: 20h Device Code: E2hTable 1. Signal Names November 19991/31This is information on a product still in production but not

4、 recommended for new designs. Figure 2B. TSOP Pin Connections Figure 2A. LCC Pin Connections Figure 2C. TSOP Reverse Pin ConnectionsDESCRIPTIONThe M29F040 is a non-volatile memory that maybe erased electrically at the block level, and pro-grammed Byte-by-Byte.The Flash Memory organisation is 512K x8

5、 bits withAddress lines A0-A18 and Data Inputs/OutputsDQ0-DQ7. Memory control is provided by ChipEnable, Output Enable and Write Enable Inputs.Erase and Program are performed through theinternal Program/Erase Controller (P/E.C.Data Outputs bits DQ7 and DQ6 provide polling ortoggle signals during Aut

6、omatic Program or Eraseto indicate the Ready/Busy state of the internalProgram/Erase Controller.Memory BlocksErasure of the memory is in blocks. There are 8uniform blocks of 64 Kbytes each in the memoryaddress space. Each block can be programmedand erased over 100,000 cycles. Each uniformblock may s

7、eparately be protected and unpro-M29F040 Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"may cause permanent damage to the device. These are stress ratings only and operation of the device at these o

8、r any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute MaximumRating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.2. Min

9、imum Voltage may undershoot to 2V during transition and for less than 20ns.3. Depends on range.Table 2. Absolute Maximum Ratings (1tected against program and erase. Block erasuremay be suspended, while data is read from otherblocks of the memory, and then resumed.Bus OperationsSeven operations can b

10、e performed by the appro-priate bus cycles, Read Array, Read ElectronicSignature, Output Disable, Standby, Protect Block,Unprotect Block, and Write the Command of anInstruction.Command InterfaceCommand Bytes can be written to a CommandInterface (C.I. latch to perform Reading (from theArray or Electr

11、onic Signature, Erasure or Pro-gramming. For added data protection, commandexecution starts after 4 or 6 command cycles. Thefirst, second, fourth and fifth cycles are used toinput a code sequence to the Command Interface(C.I. This sequence is equal for all P/E.C. instruc-tions. Command itself and it

12、s confirmation - if itapplies - are given on the third and fourth or sixthcycles.InstructionsSeven instructions are defined to perform Reset,Read Electronic Signature, Auto Program, BlockAuto Erase, Chip Auto Erase, Block Erase Suspendand Block Erase Resume. The internal Pro-gram/Erase Controller (P

13、/E.C. handles all timingand verification of the Program and Erase instruc-tions and provides Data Polling, Toggle, and Statusdata to indicate completion of Program and EraseOperations.Instructions are composed of up to six cycles. Thefirst two cycles input a code sequence to the Com-mand Interface w

14、hich is common to all P/E.C.instructions (see Table 7 for Command Descrip-tions. The third cycle inputs the instruction set upcommand instruction to the Command Interface.Subsequent cycles output Signature, Block Protec-tion or the addressed data for Read operations.For added data protection, the in

15、structions for pro-gram, and block or chip erase require further com-mand inputs. For a Program instruction, the fourthcommand cycle inputs the address and data to beprogrammed. For an Erase instruction (block orchip, the fourth and fifth cycles input a further codesequence before the Erase confirm

16、command onthe sixth cycle. Byte programming takes typically10µs while erase is performed in typically 1.0 sec-ond.Erasure of a memory block may be suspended, inorder to read data from another block, and thenresumed. Data Polling, Toggle and Error data maybe read at any time, including during th

17、e program-ming or erase cycles, to monitor the progress ofthe operation. When power is first applied or if VCC falls below VLKO , the command interface is reset toRead Array. M29F040 IL IHTable 3. Operations Table 4. Electronic Signature Table 5. Block Protection StatusDEVICE OPERATIONSignal Descrip

18、tionsAddress Inputs (A0-A18. The address inputs forthe memory array are latched during a write opera-tion. The A9 address input is used also for theElectronic Signature read and Block Protect veri-fication. When A9 is raised to VID , either a ReadManufacturer Code, Read Device Code or VerifyBlock Pr

19、otection is enabled depending on the com-bination of levels on A0, A1 and A6. When A0, A1and A6 are Low, the Electronic Signature Manufac-turer code is read, when A0 is High and A1 and A6are Low, the Device code is read, and when A1 isHigh and A0 and A6 are low, the Block ProtectionStatus is read fo

20、r the block addressed by A16, A17,A18.Data Input/Outputs (DQ0-DQ7. The data input isa byte to be programmed or a command written tothe memory Array, the Electronic Signature, theData Polling bit (DQ7, the Toggle Bit (DQ6, theError bit (DQ5 or the Erase Timer bit (DQ3. Ou-when the chip is deselected

21、or the outputs aredisabled.The Chip Enable activates thememory control logic, input buffers, decoders andreduces the power consumption to the standbycommand register and to the memory array, whileforced to VID during Block Unprotect operations. The Output Enable gates theoutputs through the data buf

22、fers during a readID level duringBlock Protect and Block Unprotect operations. This input controls writing to theCommand Register and Address and Data latches.V CC Supply Voltage. The power supply for alloperations (Read, Program and Erase.V SS Ground. VSS is the reference for all voltage measuremen

23、ts.M29F040 Notes:1.Command not interpreted in this table will default to read array mode.2. While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I.3. X = Dont Care.4.The first cycle of the RST, RBP or RSIG instruction is followed by r

24、ead operations to read memory array, Status Register or Electronic Signature codes. Any number of read cycles can occur after one command cycle.5. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h. Address bits A0 at VIH and A1, A6 at VIL will output Device code.6. Protecti

25、on Address: A0, A6 at VIL , A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection status.7. Address bits A15-A18 are dont care for coded address inputs.8.Optional, additional blocks addresses must be entered within a 80µs delay after last write ent

26、ry, timeout status can be verified through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.9.Read Data Polling or Toggle bit until Erase completes.10.A wait time of 5µs is necessary after a Reset command, if the memory is in a Block

27、 Erase status, before startingany operation.Table 6. Instructions (1,2 M29F040Memory BlocksThe memory blocks of the M29F040 are shown inFigure 3. The memory array is divided in 8 uniformblocks of 64 Kbytes. Each block can be erasedseparately or any combination of blocks can beerased simultaneously.

28、The Block Erase operationis managed automatically by the P/E.C. The opera-tion can be suspended in order to read from anyother block, and then resumed.Operations are defined as specific bus cycles andsignals which allow Memory Read, CommandWrite, Output Disable, Standby, Read Status Bits,Block Prote

29、ct/Unprotect, Block Protection Checkand Electronic Signature Read. They are shown inTables 3, 4, 5.Read. Read operations are used to output thecontents of the Memory Array, the Status Registerthe output of the memory. The Chip Enable inputalso provides power control and should be used fordevice sele

30、ction. Output Enable should be used togate data onto the output independent of the deviceselection. The data read depends on the previouscommand written to the memory (see instructionsRST and RSIG, and Status Bits.Write. Write operations are used to give InstructionCommands to the memory or to latch

31、 input data tobe programmed. A write operation is initiated whenCommands and Input Data are latched on the risingOutput Disable. The data outputs are high imped-Standby. The memory is in standby when ChipP/E.C. is Idle. The power consumption is reducedto the standby level and the outputs are high im

32、-Automatic Standby. After 150ns of inactivity andwhen CMOS levels are driving the addresses, thechip automatically enters a pseudo standby modewhere consumption is reduced to the CMOSstandby value, while outputs are still driving thebus.Electronic Signature. Two codes identifying themanufacturer and

33、 the device can be read from thememory, the manufacturers code for STMicroelec-tronics is 20h, and the device code is E2h for theM29F040. These codes allow programming equip-ment or applications to automatically match theirinterface to the characteristics of the particularmanufacturers product. The

34、Electronic Signatureis output by a Read operation when the voltageapplied to A9 is at VID and address inputs A1 andA6 are at Low. The manufacturer code is outputwhen the Address input A0 is Low and the devicecode when this input is High. Other Address inputsare ignored. The codes are output on DQ0-D

35、Q7.This is shown in Table 4.The Electronic Signature can also be read, withoutraising A9 to VID by giving the memory the instruc-tion RSIG (see below.Block Protection. Each uniform block can beseparately protected against Program or Erase.Block Protection provides additional data security,as it disa

36、bles all program or erase operations. Thismode is activated when both A9 and V ID and the block address is applied on A16-A18.Block Protection is programmed using a Presto Fprogram like algorithm. Protection is initiated on theIL . Then after a delay of 100µs, IH ends the protectionoperation. P

37、rotection verify is achieved by bringingIL IH and A9 at VID . Under these conditions, reading the data output willyield 01h if the block defined by the inputs onA16-A18 is protected. Any attempt to program orerase a protected block will be ignored by thedevice.Any protected block can be unprotected

38、to allowupdating of bit contents. All blocks must be pro-tected before an unprotect operation. Block Un-ID . The addresses inputs A6, A12, A16 must be main-tained at VIH . Block Unprotect is performed througha Presto F Erase like algorithm. Unprotect is initi-IL . After a delayIH will end theunprote

39、ction operation. Unprotect verify isIL while A6 andIH and A9 at VID . In these conditions,reading the output data will yield 00h if the blockdefined by the inputs on A16-A18 has been suc-cessfully unprotected. All combinations of A16-A18 must be addressed in order to ensure that allof the 8 uniform

40、blocks have been unprotected.Block Protection Status is shown in Table 5. M29F040 Figure 3. Memory Map and Block Address TableTable 7. CommandsInstructions and CommandsThe Command Interface (C.I. latches commandswritten to the memory. Instructions are made upfrom one or more commands to perform Read

41、Array/Reset, Read Electronic Signature, BlockErase, Chip Erase, Program, Block Erase Suspendand Erase Resume. Commands are made of ad-dress and data sequences. Addresses are latched1 to 6 cycles, the first or first three of which arealways write operations used to initiate the com-mand. They are fol

42、lowed by either further writecycles to confirm the first command or execute thecommand immediately. Command sequencingmust be followed exactly. Any invalid combinationof commands will reset the device to Read Array.The increased number of cycles has been chosento assure maximum data security. Comman

43、ds areinitialised by two preceding coded cycles whichunlock the Command Interface. In addition, forErase, command confirmation is again preceededby the two coded cycles.P/E.C. status is indicated during command execu-tion by Data Polling on DQ7, detection of Toggle onDQ6, or Error on DQ5 and Erase T

44、imer DQ3 bits.Any read attempt during Program or Erase com-mand execution will automatically output those fourbits. The P/E.C. automatically sets bits DQ3, DQ5,DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 andDQ4 are reserved for future use and should bemasked.M29F040 Table 8. Status RegisterData Polling b

45、it (DQ7. When Programming op-erations are in progress, this bit outputs the com-plement of the bit being programmed on DQ7.During Erase operation, it outputs a 0. After com-pletion of the operation, DQ7 will output the bit lastprogrammed or a 1 after erasing. Data Polling isvalid only effective duri

46、ng P/E.C. operation, that isat the address being programmed or at an addresswithin the block being erased. If the byte to beprogrammed belongs to a protected block the com-mand is ignored. If all the blocks selected for era-sure are protected, DQ7 will set to 0 for about100µs, and then return t

47、o previous addressedmemory data. See Figure 9 for the Data Pollingflowchart and Figure 10 for the Data Polling wave-forms.Toggle bit (DQ6. When Programming operationsare in progress, successive attempts to read DQ6will output complementary data. DQ6 will toggleThe operation is completed when two suc

48、cessivereads yield the same output data. The next readwill output the bit last programmed or a 1 aftererasing. The toggle bit is valid only effective duringErase. If the byte to be programmed belongs to aprotected block the command will be ignored. If theblocks selected for erasure are protected, DQ

49、6 willtoggle for about 100µs and then return back to Read. See Figure 11 for Toggle Bit flowchart andFigure 12 for Toggle Bit waveforms.Error bit (DQ5. This bit is set to 1 by the P/E.Cwhen there is a failure of byte programming, blockerase, or chip erase that results in invalid databeing progr

50、ammed in the memory block. In case oferror in block erase or byte program, the block inwhich the error occured or to which the pro-grammed byte belongs, must be discarded. Otherblocks may still be used. Error bit resets after Reset(RST instruction. In case of success, the error bitwill set to 0 duri

51、ng Program or Erase and to validdata after write operation is completed.M29F040 Figure 4. AC Testing Input Output Waveform Figure 5. AC Testing Load CircuitNote:1. Sampled only, not 100% tested.Table 10. Capacitance (1 (TA = 25 °C, f = 1 MHz Erase Timer bit (DQ3. This bit is set to 0 by theP/E.

52、C. when the last Block Erase command hasbeen entered to the Command Interface and it isawaiting the Erase start. When the wait period isfinished, after 80 to 120µs, DQ3 returns back to 1.Coded Cycles. The two coded cycles unlock theCommand Interface. They are followed by a com-mand input or a c

53、omand confirmation. The codedcycles consist of writing the data AAh at address5555h during the first cycle and data 55h at address2AAAh during the second cycle. Addresses arecycles happen on first and second cycles of thecommand write or on the fourth and fifth cycles.Read Array/Reset (RST instructi

54、on. The Resetinstruction consists of one write operation givingthe command F0h. It can be optionally precededby the two coded cycles. A wait state of 5µs beforeread operations is necessary if the Reset command is applied during an Erase operation.Read Electronic Signature (RSIG instruction.This

55、 instruction uses the two coded cycles followedby one write cycle giving the command 90h toaddress 5555h for command setup. A subsequentread will output the manufacturer code, the devicecode or the Block Protection status depending onthe levels of A0, A1, A6, A16, A17 and A18. Themanufacturer code,

56、20h, is output when the ad-dresses lines A0, A1 and A6 are Low, the devicecode, E2h is output when A0 is High with A1 and A6 Low.Table 9. AC Measurement ConditionsM29F040 Table 11. DC Characteristics(TA = 0 to 70 °C, 20 to 85°C, 40 to 85°C or 40 to 125°C; VCC = 5V ± 10%Read

57、Block Protection (RBP instruction. The use of Read Electronic Signature (RSIG commandalso allows access to the Block Protection statusverify. After giving the RSIG command, A0 and A6are set to VIL with A1 at VIH , while A16, A17 andA18 define the block of the block to be verified. Aread in these con

58、ditions will output a 01h if block isprotected and a 00h if block is not protected.This Read Block Protection is the only valid way tocheck the protection status of a block. Neverthe-less, it must not be used during the Block Protectionphase as a method to verify the block protection.Please refer to

59、 Block Protection paragraph.Chip Erase (CE instruction. This instruction usessix write cycles. The Erase Set-up command 80his written to address 5555h on third cycle after thetwo coded cycles. The Chip Erase Confirm com-mand 10h is written at address 5555h on sixth cycleafter another two coded cycles. If the second com-mand given is not an erase confirm or if the codedcycles are wrong, the instruction abo