全自动洗衣机控制系统设计文献翻译

1、AT89C51的概述1 AT89C51 应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车 发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适 合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。健 壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具 环境保证了高可靠性和低市场风险。In tel平台工程部门开发了一种面向对象的用于验 证它的AT89C51汽车单片机多线性测试环境。这种环境的目标不仅是为 AT89C51汽车 单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将

2、 来的单片机。开发的这种环境连接了 AT89C51。本文讨论了这种测试环境的设计和原理， 它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51。1.1介绍8位AT89C51 CHMOS工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51单片机典型的应用是高速事件控制系统。商业应用包括调制解调器，电动机控 制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。汽车工业把MCS51单片机用于发动机控制系统，悬挂系统和反锁制动系统。AT89C51尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反 锁制动和稳定性控制应用。由于这些决定

3、性应用，市场需要一种可靠的具有低干扰潜伏 响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能 力，具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的 经济和法律风险是很高的。一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁 制动系统，错误将是财力上所禁止的。重新设计的费用可以高达500K美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂 贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓 和这些问题，在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级 别上的综合测

4、试是必需的。In tel Cha ndler平台工程组提供了各种单片机和处理器的系统 验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了 能够在设备上执行的测试类型。1.2 AT89C51提供以下标准功能4k字节FLASH闪速存储器，128字节内部RAM，32个I/O 口线，2个16位定 时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电 路。同时，AT89C51降至OHz的静态逻辑操作，并支持两种可选的节电工作模式。空 闲方式体制CPU的工作，但允许 RAM，定时/计数器，串行通信口及中断系统继续工 作。掉电方式保存RAM中的内容，但振荡器

5、体制工作并禁止其他所有不见工作直到下 一个硬件复位。£图1 AT89C51方框图1.3引脚功能说明Vcc :电源电压GND:地P0 口： P0 口是一组8位漏极开路型双向I/O 口，也即地址/数据总线复用。作为 输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写一1可作为高 阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。在Flash编程时，P0 口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1 口： P1是一个带内部上拉电阻的 8位双向I/O 口，P1的输出缓冲级

6、可驱动 （吸收或输出电流）4个TTL逻辑门电路。对端口写 一1,通过内部的上拉电阻把端口 拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚 被外部信号拉低时会输出一个电流 （IIL） o Flash编程和程序校验期间，P1接受低8位 地址。P2 口： P2是一个带有内部上拉电阻的 8位双向I/O 口，P2的输出缓冲级可驱 动（吸收或输出电流）4个TTL逻辑门电路。对端口写一1,通过内部的上拉电阻把端 口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引 脚被外部信号拉低时会输出一个电流（IIL ） o在访问外部程序存储器或 16位四肢的外 部

7、数据存储器（例如执行 MOVX DPTR指令）时，P2 口送出高8位地址数据，在访 问8位地址的外部数据存储器（例如执行MOVX RI指令）时，P2 口线上的内容（也 即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。Flash编 程和程序校验时，P2也接收高位地址和其他控制信号。P3 口： P3是一个带有内部上拉电阻的 8位双向I/O 口，P3的输出缓冲级可驱 动（吸收或输出电流）4个TTL逻辑门电路。对端口写一1,通过内部的上拉电阻把端 口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引 脚被外部信号拉低时会输出一个电流 （IIL ）0 P3

8、 口还接收一些用于Flash闪速存储器编 程和程序校验的控制信号。RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位ALE/PROG :当访问外部程序存储器或数据存储器时，ALE （地址锁存允许）输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的 1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是，每 当访问外部数据存储器时将跳过一个 ALE脉冲。对Flash存储器编程期间，该引脚还 用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH 单元DO位置位，可禁止 ALE操作。该

9、位置位后，只有一条 MOVX和MOVC指令 ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无 效。PSEN:程序存储允许输出是外部程序存储器的读选通型号，当89C51由外部存储 器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的 PSEN信号不出现。EA/VPP :外部访问允许。欲使CPU仅访问外部程序存储器（地址0000HFFFFH）， EA端必须保持低电平（接地）。需注意的是：如果加密位 LB1被编程，复位时内部会 锁存EA端状态。如EA端为高电平（接Vcc端），CPU则执行内部程序存储器中的 指

10、令。Flash存储器编程时，该引脚加上+12v的编程允许电源Vpp，当然这必须是该器 件使用12v编程电压Vpp。XTAL1 :振荡器反相放大器及内部时钟发生器的输入端。XTAL2 :振荡器反相放大器的输出端。89C51中有一个用于构成内部振荡器的高 增益反相放大器，引脚 XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放 大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。外接石英晶体或陶瓷谐振器及电容 C1、C2接在放大器的反馈回路中构成并联振 荡电路。对电容C1、C2虽没有十分严格的要求，但电容容量的大小会轻微影响振荡频 率的高低、振荡器工作的稳定

11、性、起振的难易程度及温度稳定性，如果使用石英晶体， 我们推荐电容使用30Pf±0 Pf,而如使用陶瓷谐振器建议选择 40Pf±0Pf。用户也可以 采用外部时钟。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端XTAL2则悬空。掉电模式：在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被 执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。推出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在Vcc恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡 器重启动并稳定工作。89C51的程

12、序存储器阵列是采用字节写入方式编程的，每次写入 一个字符，要对整个芯片的EPROM程序存储器写入一个非空字节，必须使用片擦除的 方法将整个存储器的内容清楚。2编程方法编程前，设置好地址、数据及控制信号，编程单元的地址加在P1 口和P2 口的P2.0-P2.3（ 11位地址范围为0000H0FFFH）,数据从P0 口输入，引脚 P2.6、P2.7 和P3.6、P3.7的电平设置见表6, PSEB为低电平，RST保持高电平，EA/Vpp弓I脚是 编程电源的输入端，按要求加上编程电压，ALE/PROG引脚输入编程脉冲（负脉冲）。编程时，可采用4 20MHz的时钟振荡器，89C51编程方法如下：在地址

13、线上加上要 编程单元的地址信号在数据线上加上要写入的数据字节。激活相应的控制信号。在高电 压编程方式时，将 EA/Vpp端加上+12v编程电压。每对Flash存储阵列写入一个字节 或每写入一个程序加密位，加上一个ALE/PROG编程脉冲。改变编程单元的地址和写入的数据，重复15步骤，知道全部文件编程结束。每个字节写入周期是自身定时的， 通常约为1.5ms。数据查询89C51单片机用数据查询方式来检测一个写周期是否结束， 在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最高位（P0.7）是原来写入字节的最高位的反码。写周期开始后，可在任意时刻进行数据查询。2.1 Ready/Busy

14、字节编程的进度可通过 Ready/Busy输出信号检测，编程期间，ALE变为高电平一H| 后P3.4 （Ready/Busy）端被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变 为高电平表示准备就绪状态。程序校验：如果加密位LB、LB2没有进行编程，则代码数据可通过地址和数据线 读回原编写的数据，采用下图的电路，程序存储器的地址由P1 口和P2 口的P2.0-P2.3 输入，数据由P0 口读出，P206、P2.7和P3.6、P3.7的控制信号见表6，PSEN保持低 电平，ALE、EA和RST保持高电平。校验时，P0 口必须接上10k左右的上拉电阻。ADWOOCXihWFFFH- A1

15、1SEC FlASHPR9M删I4_MX-ES TADLE924 MH£二P1%R2 0 P2.3 P0P2JBP2 7ALEP3J8P3 7JCWL2EAXWL1RSTPSEN图2编程电路2+iXO；+i>FFFH阿-A11»St E FU$HPR>.GfiM4JlNG-WX-ES TABLE珍 Mtt X口匚PIVKP2.0 -P2.3 因P2.6P2 74LEP9.SP3.7WTBI <5r j.A IRuRSTPSEtinirttiGND图3校验电路側 DAT* f |U$E IC'KPULLJUPSj2.2芯片擦除利用控制信号的正确组合(

16、表6)并保持ALE/PROG引脚10ms的低电平脉冲宽度即 可将EPROM阵列(4k字节)和三个加密位整片擦除，代码阵列在片擦除操作中将任何非 空单元写入II 1这步骤需在编程之前进行。2.3读片内签名字节89C51单片机内有3个签名字节,地址为030H、031H和032H。于声明该器件的 厂商、号和编程电压。读签名字节的过程和单元030H、031H和032H的正常校验相仿, 只需要将P3.6和P3.7保持低电平，返回值意义如下：(030H) = 1EH声明产品由ATMEL公司制造(031H) = 51H声明为89C51单片机。(032H) = FFH声明为12V编程电压。(032H) = 0

17、5H声明为5编程电压。2.4编程接口采用控制信号的正确组合可对 Flash闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。微机 接口实现两种信息形式的交换。在计算机之外，由电子系统所处理的信息以一种物理信 号形式存在，但在程序中，它是用数字表示的。任一接口的功能都可分为以某种形式进 行数据库变换的一些操作，所以外部和内部形式的转换是由许多步骤完成的。模拟-数字转换器（ADC ）用来将连续变化信号变成相应的数字量，这数字量可是可能性的二进 制数值中的一固定值。如果传感器输出不是连续变化的，就不需模拟-数字转换。这种情况下，信号调理单

18、元必须将输入信号变换成为另一信号，也可直接与接口的下一部分，即微计算机本身的输入输出单元相连接。输出接口采用相似的形式，明显的差别在于信 息流的方向相反；是从程序到外部世界。这种情况下，程序可称为输出程序，它监督接 口的操作并完成数字-模拟转换器（DAC ）所需数字的标定。该子程序依次送出信息给 输出器件，产生相应的电信号，由 DAC转换成模拟形式。最后，信号经调理（通常是 放大）以形成适应于执行器操作的形式。在微机电路中使用的信号几乎总是太小而不能 被直接地连到¥卜部世界II,因而必须用某种形式将其转换成更适宜的形式。接口电路部 分的设计是使用微机的工程师所面临最重要的任务之一。我

19、们已经了解到微机中，信号 以离散的位形式表示。当微机要与只有打开或关闭操作的设备相连时，这种数字形式是 最有用的，这里每一位都可表示一开关或执行器的状态。为了解决实际问题，一个单片 机不仅包括CPU,程序和数据存储器，另外，它必须含有通过 CPU访问外部信息的硬 件。一旦CPU收集到数据信息和流程，它必须能够改变外部领域的一部分，这些硬件 设备称作外围设备，它们是 CPU通往外部的窗口。单片机可利用外围设备中最基本的用于一般用途的I/O接口，每个I/O接口既可作为输入端又可作为输出端，每个I/O接口的功能取决与程序初始化阶段对数据方位寄存 器相应位进行置一和清零操作，通过 CPU指令对数据寄存

20、器相应位进行置一和清零来 置一和清零输出端口，同样输入端口逻辑位也可以通过CPU指令访问。一些类型的串行口单元允许CPU与外部设备进行串口通信，用串口位代替平行位进行通信需要少许 的I/O 口，这样使通信费用降低但速度也相对慢些。串口传送可以同步也可以异步。来源于：AT89C51的概况附：英文原文The General Situation of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-c

21、o ntrol systems, air con diti oner con trol systems, automotive engine and among others. The high process ing speed and enhan ced peripheral set of these microc on trollers make them suitable for such high-speed event-based applications. However, these critical application doma ins also require that

22、 these microc on trollers are highly reliable. The high reliability and low market risks can be en sured by a robust testi ng process and a proper tools en vir onment for the validati on of these microc on trollers both at the comp onent and at the system level. In tel Plaform Engin eeri ng departme

23、 nt developed an object-orie nted multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microc on trollers, but to develop an en vir onment which can

24、be easily exte nded and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software

25、 en vir onmen tal comp onen ts, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microco ntrollers are desig ned to han dle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed eve nt con trol systems. Commercial applicati o

26、ns in clude modems,motor-c on trol systems, prin ters, photocopiers, air con diti oner con trol systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engin e-c on trol systems, airbags, suspe nsion systems, and an tilock brak ing systems (ABS). The AT89

27、C51 is especially well suited to applicati ons that ben efit from its process ing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dyn amic suspe nsion, an tilock brak ing, and stability con trol applicatio ns. Because of these critical application

28、s, the market requires a reliable cost-effective controller with a low in terrupt late ncy resp on se, ability to service the high nu mber of time and eve nt drive n integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financ

29、ial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means

30、2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the comp onent. To mitigate these problem

31、s, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage con diti on s.This complete and thorough validati on n ecessitates not only a well-defi ned process but also a proper environment an

32、d tools to facilitate and execute the mission successfully.Intel Chan dler Platform Engin eeri ng group provides post silic on system validati on (SV) of various micro-co ntrollers and processors. The system validatio n process can be broke n in to three major parts.The type of the device and its ap

33、plicati on requireme nts determ ine which types of testi ng are performed on the device.1.2 The AT89C51 provides the following standard features4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-ch

34、ip oscillator and clock circuitry .In additi on, the AT89C51 is desig ned with static logic for operati on dow n to zero freque ncy and supports two software selectable power sav ing modes. The Idle Mode stops the CPU while allowi ng the RAM, timer/c oun ters,serial port and in terrupt sys -tem to c

35、ontinue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -atordisabling all other chip functions until the next hardware reset.呷 4 > pcltFigure 1 Block Diagram1.3Pin DescriptionVCC Supply voltage.GND Grou nd.Port 0: Port 0 is an 8-bit open-drain bi-directional I/O por

36、t. As an output port, each pin cansink eight TTL in puts. When 1s are writte n to port 0 pins, the pins can be used as highimpeda nce in puts.Port 0 may also be con figured to be the multiplexed loworder address/data busduri ng accesses to exter nal program and data memory. I n this mode P0 has in t

37、ernalpullups.Port 0 also receives the code bytes duri ng Flash program min g,a nd outputs the codebytes duri ng program verificati on.Exter nalpullups are required duri ngprogramverificati on.Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/

38、so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 1 pins that are externally being pulled low will source current (IIL) becauseof the internal pullups.Port 1 also receives the low-order address bytes

39、duri ng Flash program ming and verificati on.Port 2： Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as in puts. As in puts, Port 2

40、 pins that are exter nally being pulled low will source curre nt (IIL) because of the internal pullups. Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and duri ng accesses to Port 2 pi ns that are externally being pulled low will source curre nt (IIL) because

41、of the internal pullups.Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and during accessesto external data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data mem

42、ory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Fun cti on Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port

43、 3 outputbuffers can sin k/sou -rce four TTL in puts.Whe n 1s are writte n to Port 3 pi ns they are pulled high by the internal pullups and can be used as in puts. As in puts,Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the pullups.Port 3 also serves the fu

44、nctions of various special featuresof the AT89C51 as listed below:RST: Reset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROG : Address Latch Enable output pulse for latching the low byte of the address duri ngaccesses to exter nal memory.

45、This pin is also the program pulse in put (PROG) duri ng Flash programmingn normal operation ALE is emitted at a constant rate of 1/6 the oscillator freque ncy,a nd may be used for exter nal tim ing or clock ing purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external D

46、ataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN

47、： Program Store Enable is the read strobe to external program memory. When theAT89C51 is executi ng code from exter nal program memory, PSEN is activated twiceeach mach ine cycle, except that two PSEN activati ons are skipped duri ng each access toexter nal data memory.EA/VPP : External Access Enabl

48、e. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be intern ally latched on reset.EA should be strapped to VCC for internal program executio ns. This p

49、in alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1 : In put to the inverting oscillator amplifier and in put to the internal clock operat in gcircuit.XTAL2 : Output from the in vert ing oscillator amplifier.Oscillator Charact

50、eristicsXTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifierwhich can be con figured for use as an on-chip oscillator, as show n in Figure 1. Either aquartz crystal or ceramic res on ator may be used. To drive the device from an exter nalclock source, XTAL2 should be le

51、ft unconnected while XTAL1 is driven as shown in Figure 2.There are no requireme nts on the duty cycle of the external clock sig nal, since the in put to the in ternal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be ob

52、served. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remai n active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers rema in un cha nged during this mode. The idle mode can be terminated by any enabled

53、interrupt or by a hardware reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device no rmally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal

54、RAM in this eve nt, but access to the port pins is not in hibited. To elim in ate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down Mo

55、de : In the power-down mode, the oscillator is stopped, and the in structi on that inv okes power-dow n is the last in structio n executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-dow n is a hardware reset.

56、Reset redefi nes the SFRs but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its normal operati ng level and must be held active long eno ugh to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in eit

57、her programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore program ming the AT89C51, the address, data and con trol sig nals should be set up accord ing to the Flash program ming mode table

58、and Figure 3 and Figure 4. To program the AT89C51, take the followi ng steps.1. In put the desired memory locati on on the address lin es.2. In put the appropriate data byte on the data lin es. 3. Activate the correct comb in ati on of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more tha n 1.5 ms. Repeat steps 1 through