FinFET(鳍式场效晶体管)工艺技术IntroductiontoFinFETtechnology

1、Thisisthefirstofamulti-partseries,tointroduceFinFETtechnologytoSemiWikireaders.Thesearticleswillhighlightthetechnologyskeycharacteristics,anddescribesomeoftheadvantages,disadvantages,andchallengesassociatedwiththistransition.TopicsinthisserieswillincludeFinFETfabrication,modeling,andtheresultingimpa

2、ctuponexistingEDAtoolsandflows.(And,ofcourse,feedbackfromSemiWikireaderswillcertainlyhelpinfluencesubsequenttopics,aswell.)ScalingofplanarFETshascontinuedtoprovideperformance,power,andcircuitdensityimprovements,uptothe22/2Onmprocessnode.AlthoughactiveresearchonFinFETdeviceshasbeenongoingformorethana

3、decade,theirusebyaproductionfabhasonlyrecentlygainedadoption.Thebasiccross-sectionofasingleFinFETisshowninFigure1.Thekeydimensionalparametersaretheheightandthicknessofthefin.Aswithplanardevices,thedrawngatelength(notshown)separatingthesourceanddrainnodesisa“criticaldesigndimension”.Aswillbedescribed

4、inthenextinstallmentinthisseries,theh_finandt_finmeasuresaredefinedbythefabricationprocess,andarenotdesignparameters.flObulksiliconsubstrateFigure1.FinFETcross-section,withgatedielectriconfinsidewallsandtop,andbulksiliconsubstrateTheFinFETcross-sectiondepictsthegatespanningbothsidesandthetopofthefin

5、.Forusedtorealizeansimplicity,asinglegatedielectriclayerisshown,abstractingthecomplexmulti-layerdielectricsusedtorealizean“effective”oxidethickness(EOT).Similarly,asimplegatelayerisshown,abstractingthemultiplematerialscomprisingthe(metal)gate.Intheresearchliterature,FinFETshavealsobeenfabricatedwith

6、athickdielectriclayerontop,limitingthegateselectrostaticcontrolonthefinsilicontojustthesidewalls.Someresearchershaveevenfabricatedindependentgatesignals,oneforeachfinsidewall-inthiscase,onegateisthedeviceinputandtheotherprovidestheequivalentofFET“backbiascontrol.Fortheremainderofthisseries,thediscus

7、sionwillfocusonthegateconfigurationshown,withathingatedielectriconthreesides.(Inteldenotesthisas-Gate”inllnieirrecentIvyBridgeproductannouncements.)Duetothemorecomplexfabricationsteps(andcosts)of-gate”ualand“independent-gate”devices,theexpectationisthatthesealternativeswillnotreachhighvolumeproducti

8、on,despitesomeoftheiruniqueelectricalcharacteristics.AnotherfabricationalternativeistoprovideanSOIsubstrateforthefin,ratherthanthebulksiliconsubstrateshowninthefigure.Inthisseries,thefocuswillbeonbulkFinFETs,althoughdifferencesbetweenbulkandSOIsubstratefabricationwillbehighlightedinseveralexamples.F

9、igure2.Multiplefinsinparallelspaceds_finapart,commongateinputFigure2illustratesacross-sectionofmultiplefinsconnectedinparallel,withacontinuousgatematerialspanningthefins.TheSourceandDrainnodesoftheparallelfinsarenotvisibleinthiscross-sectionsubsequentfigureswillshowthelayoutandcross-sectionviewofpar

10、allelS/Dconnections.Theuseofparallelfinstoprovidehigherdrivecurrentintroducesathirdparameter,thelocalfinspacing(s_fin).Simplistically,theeffectivedevicewidthofasinglefinis:(2*h_fin+t_fin),thetotalmeasureofthegateselectrostaticcontroloverthesiliconchannel.Thegoalofthefabricationprocesswouldbetoenable

11、asmallfinspacing,sothattheFinFETexceedsthedevicewidththataplanarFETprocesswouldotherwiseprovide:s_fin(2*h_fin+t_fin)SubsequentdiscussionsinthisserieswillreviewsomeoftheuniquecharacteristicsofFinFETs,whichresultinbehaviorthatdiffersfromthesimple(2*h+t)channelsurfacecurrentwidthmultiplier.Theidealtopo

12、logyofa“tall,narrow”finforoptimumcircuitdensityismitigatedbythedifficultiesandvariationsassociatedwithfabricatingahighaspectratiofin.Inpractice,anaspectratioof(h_fin/t_fin2:1)ismorerealistic.OneimmediateconsequenceofFinFETcircuitdesignisthattheincrementsofdevicewidtharelimitedto(2h+t),byaddinganothe

13、rfininparallel.Actually,duetotheuniquemeansbywhichfinsarepatterned,acommondevicewidthincrementwillbe(2*(2h+t),aswillbediscussedinthenextinstallmentinthisseries.ThequantizationofdevicewidthinFinFETcircuitdesignisdefinitelydifferentthanthecontinuousvaluesavailablewithplanartechnology.However,mostlogic

14、cellsalreadyuselimiteddevicewidthsanyway,andcustomcircuitoptimizationalgorithmstypicallysupport“snapping”toafixedsetofavailablewidthvalues.SRAMarraysandanalogcircuitsarethemostimpactedbythequantizedwidthsofFinFETs-especiallySRAMbitcells,wherehighlayoutdensityandrobustreadability/writeabilitycriteria

15、bothneedtobesatisfied.Theunderlyingbulksiliconsubstratefromwhichthefinisfabricatedistypicallyundoped(i.e.,averylowimpurityconcentrationpercm*3).TheswitchinginputthresholdvoltageoftheFinFETdevice(Vt)issetbytheworkfunctionpotentialdifferencesbetweenthegate,dielectric,and(undoped)siliconmaterials.Altho

16、ughthesiliconfinimpurityconcentrationiseffectivelyundoped,theprocessneedstointroduceimpuritiesunderthefinasachannelstop,toblock“punchthrough”currentbetweensourceanddrainnodesfromcarriersnotcontrolledelectrostaticallybythegateinput.Theoptimummeansofintroducingthepunchthrough-stopimpurityregionbelowth

17、efin,withoutsubstantiallyperturbingthe(undoped)concentrationinthefinvolumeitself,isanactiveareaofprocessdevelopment.ModernchipdesignsexpecttohavemultipleVtdeviceofferingsavailable-e.g.,a“standard”Vt,a“high”Vt,anda“lowto”enVatble-cell-swapoptimizationsthattrade-offperformanceversus(leakage)power.Fore

18、xample,thedelayofanSVT-basedlogiccircuitpathcouldbeimprovedbyselectivelyintroducingLVT-basedcells,attheexpenseofhigherpower.Inplanarfabricationtechnologies,multipleVtdeviceofferingsarereadilyavailable,usingasetofthreshold-adjustingimpurityimplantsintomaskedchannelregions.InFinFETtechnologies,differe

19、ntdevicethresholdswouldbeprovidedbyanalternativegatemetallurgy,withdifferentworkfunctionpotentials.Theavailabilityofmultiple(nFETandpFET)devicethresholdsisagoodexampleofthetradeoffsbetweenFinFETsandplanardevices.Inaplanartechnology,thecostofadditionalthresholdofferingsisrelativelylow,asthecostofanad

20、ditionalmaskingstepandimplantisstraightforward.However,themanufacturingvariationinplanardeviceVtsdueto“channelrandomdopantfluctuation(RDF)fromtheimplantsishigh.ForFinFETs,thecostofadditionalgatemetallurgyprocessingformultipleVtsishigher-yet,noimpurityintroductionintothechannelisrequired,andthus,litt

21、leRDF-basedvariationismeasured.(Cost,performanee,andstatisticalvariationcomparisonswillcomeuponseveraloccasionsinthisseriesofarticles.)Thelowimpurityconcentrationinthefinalsoresultsinlesschannelscatteringwhenthedeviceisactive,improvingthecarriermobilityanddevicecurrent.Conversely,FinFETsintroduceoth

22、ersourcesofvariation,notpresentwithplanardevices.Thefinedge“roughness”willresultinvariationindeviceVtanddrivecurrent.(Chemicaletchstepsthatareselectivetothespecificsiliconcrystalsurfaceorientationofthefinsidewallareusedtohelpreduceroughness.)ThecharacteristicsofbothplanarandFinFETdevicesdependuponGa

23、teEdgeRoughness,aswell.ThefabricationofthegatetraversingthetopologyoverandbetweenfinswillincreasetheGERvariationforFinFETdevices,asshowninFigure3.Figure3.SEMcross-sectionofmultiplefins.Gateedgeroughnessoverthefinishighlightedintheexpandedinsetpicture.FromBaravelli,etal,ImpactofLineEdgeRoughnessandRa

24、ndomDopantFluctuationonFinFETMatchingPerformanee”,IEEETransactionsonNanotechnology,v.7(3),May2008.ThenextentryinthisserieswilldiscusssomeoftheuniquefabricationstepsforFinFETs,andIntroductiontohowthesestepsinflueneedesign,layout,andDesignforManufacturability:FinFETtechnologyPartIIThemajorprocesssteps

25、infabricatingsiliconfinsareshowninFigures1through3.ThestepthatdefinesthefinthicknessusesSidewallImageTransfer(SIT).Low-pressurechemicalvapor(isotropic)depositionprovidesauniquedielectricprofileonthesidewallsofthesacrificialpatternedline.Asubsequent(anisotropic)etchofthedielectricretainsthesidewallma

26、terial(Figure1).Reactiveionetchingofthesacrificiallineandtheexposedsubstrateresultsinsiliconpedestals(Figure2).Depositionofadielectrictocompletelyfillthevolumebetweenpedestalsisfollowedbyacontrolledetch-backtoexposethefins(Figure3).deposrtedCVDdielectncsacrificialSfTpatternS!Tsidewallsafteranisotrop

27、icEtchSisubstrateFigure1.Cross-sectionofsidewallsonsacrificiallinesafterCVDetch.SisubstrateJSipedestalsafterRIEetchofsiliconusingSITFigure2.Cross-sectionofsiliconpedestalsafterRIEetch,usingSidewallImageTransfergateFigure3.Cross-sectionofsiliconfinsafteroxidedepositonandetch-back,andgatedepositon.sil

28、ieonfinsafteroxidedepositionandetch-back(gateoxideonfinnotshown)fieldoxideLow-pressuredielectricdepositiontocreatesidewallsonapolysiliconlineisawell-knowntechnique-itiscommonlyusedtoseparate(deep)source/drainimplantareasfromtheplanarFETtransistorchannel.FinFETfabricationextendsthistechniquetopattern

29、definitionforsiliconfinetching.ThereisnophotolithographystepassociatedwithSIT,justthepatterningofthesacrificiallines.Asaresult,thefinthicknesscanbesmallerthanthephotolithographicminimumdimensions.Thefinthicknessisdefinedbywell-controlleddielectricdepositionandetchingstepsratherthanphotoresistpattern

30、ing,reducingthemanufacturingvariation.However,thereisvariationinfinheight,resultingfrom(local)variationsintheetch-backrateofdielectricremoval.(ForFinFETsonanSOIsubstrate,thefinheightisdefinedbythesiliconlayerthickness,withanaturalsiliconetch-stopattheinsulatorinterfaceincontrasttothetimed-etchfinhei

31、ghtforbulksubstratepedestals.)ThereareseveralcharacteristicstonoteaboutSITtechnology.Nominally,finscomeinpairsfromthetwosidewallsofthesacrificialline.Addingfinsinparalleltoincreasedrivecurrenttypicallyinvolvesaddingapairoffins:delta_w=(2*(2*h_fin+t_fin).To“cut”fins,amaskedsiliconetchingstepisrequire

32、d.Therearetwoconsiderationsforcuttingfins.Thefirstinvolvesbreakinglongfinsintoindividualpairs.Theotheristocreateanisolatedfin,byremovingitsSIT-generatedneighbor.Criticalcircuitsthatrequirehighdensityand/ordifferentdevicesizingratiosmayjustifytheneedforisolatedfinpatterning-e.g.,SRAMbitcells.Compared

33、tocutting,isolatedfinpatterningmayinvolvedifferentdesignrulesandseparate(critical)lithographysteps,andthusadditionalcosts.Additionalprocessstepsarerequiredtointroduceimpuritiesoftheappropriatetypebelowthefintoprovideapunchthroughstop(PTS),ensuringthereisnodirectcurrentpathbetweendrainandsourcethatis

34、notelectrostaticallycontrolledbythegateinput.Thedielectricbetweenpedestalsthatremainsafteretch-backservesasthefieldoxide,asdenotedinFigure3.Thegatematerialtraversingbetweenparallelfinsiswell-separatedfromthesubstrate,minimizingtheCgxparasiticcapacitance.Theuniformityandcontrolofthefinalfindimensions

35、areimportantprocesscharacteristics,forboththefinthicknessandfincornerprofiles.(Theprofileofthepedestalbelowthefinislesscritical,andmaybequitetapered,asshowninFigure3.)Tolerancesinthefinthicknessarisefromvariationsinthevertical,anisotropicSITsiliconetch.Thefinthicknessatthebottomisalsodependentuponth

36、euniformityoftheetch-backthegoalistominimizeanydielectric“foot”remainingatthebottomofthefin.Aswillbediscussedinthenextseriesinstallment,variationsint_finhavesignificantimpactuponthetransistormodel.Thetopcornerprofilesalsohaveanimpactuponthetransistorbehavior,astheelectricfieldsfromthegatetothesilico

37、nfinareconcentratedinthisregion,originatingfromboththesidewallandtopgatematerials.Gatepatterningfollowsconventionalphotolithographicsteps,althoughtherecentintroductionofmetalgatematerialshascertainlyaddedtothecomplexity,especiallyasthegatemustnowtraverseconformallyoverparallelfins.AswithaplanarFETte

38、chnology,thegatelengthisthecriticaldimensionthatistypicallyquotedasthebasisfortheprocessnode-e.g.,20nm.IncontrasttoplanarFETtechnologies,providingmultipleFinFETthresholdvoltage(Vt)offeringsrequiressignificantadditionalprocessengineering.ThethresholdofanyFETisafunctionoftheworkfunctionpotentialdiffer

39、encesbetweenthegate,dielectric,andsiliconsubstrateinterfaces.InplanarFETs,multipleVtofferingsarereadilyprovidedbyshallow(masked)impurityimplantsintothesubstratepriortogatedeposition,adjustingtheworkfunctionpotentialbetweendielectricandchannel.However,thevariationinthe(verysmall)dosageofimpuritiesint

40、roducedintheplanarchannelresultsinsignificantVtvariation,duetorandomdopantfluctuation(RDF).WithFinFETs,thereisongoingprocessdevelopmenttoprovidedifferentmetalgatecompositions(andthus,metal-to-dielectricworkfunctions)asthepreferredmethodforVtadjust.Theadvantageofusingmultiplegatemetalswillbetoreducet

41、heRDFsourceofVtvariationsubstantially,ascomparedtoimplantinga(very,verysmall)impuritydosageintothefinvolume.Thedisadvantageistheadditionalprocesscomplexityandcostofprovidingmultiplemetalgatecompositions.AnotherkeyFinFETprocesstechnologydevelopmentisthefabricationofthesource/drainregions.Aswasmention

42、edinthefirstseriesinstallment,thesiliconfiniseffectivelyundoped.Althoughadvantageousforthedevicecharacteristics,theundopedfinresultsinhighseriesresistanceoutsidethetransistorchannel,whichwouldotherwisenegatethedrivecurrentbenefitsoftheFinFETtopology.ToreducetheRsandRdparasitics,aspaceroxideisdeposit

43、edontheFinFETgatesidewalls,inthesamemannerassidewallswerepatternedearlierforSITfinetching.Toincreasethevolumeofthesource/drain,asiliconepitaxygrowth(SEG)stepisused.TheexposedS/Dregionsoftheoriginalfinserveasthe“seed”forepitaxialgrowth,separatedfromtheFinFETgatebythesidewallspacer.Figure4showsthesour

44、ce/draincross-sectionaftertheSEGstep.CurrentDensity(Afcm2)1E6E5IJsilicideFigure4.Crosssectionofsource/drainregion,afterepitaxialgrowth.Originalfinisinblue-notethefacetedgrowthvolume.ThecurrentdensityintheS/Dpastthedevicechanneltothesilicidetopisverynon-uniform.FromKawasaki,etal,IEDM2009,p.289-292.Theincorporationofimpuritiesoftheappropriatetype(fornFETorpFET)duringepitaxialgrowthreducestheS/Dresistivitytoamoretolerablelevel.Theresistivityisfurtherredu