




版权说明:本文档由用户提供并上传,收益归属内容提供方,若内容存在侵权,请进行举报或认领
文档简介
1、Thisisthefirstofamulti-partseries,tointroduceFinFETtechnologytoSemiWikireaders.Thesearticleswillhighlightthetechnologyskeycharacteristics,anddescribesomeoftheadvantages,disadvantages,andchallengesassociatedwiththistransition.TopicsinthisserieswillincludeFinFETfabrication,modeling,andtheresultingimpa
2、ctuponexistingEDAtoolsandflows.(And,ofcourse,feedbackfromSemiWikireaderswillcertainlyhelpinfluencesubsequenttopics,aswell.)ScalingofplanarFETshascontinuedtoprovideperformance,power,andcircuitdensityimprovements,uptothe22/2Onmprocessnode.AlthoughactiveresearchonFinFETdeviceshasbeenongoingformorethana
3、decade,theirusebyaproductionfabhasonlyrecentlygainedadoption.Thebasiccross-sectionofasingleFinFETisshowninFigure1.Thekeydimensionalparametersaretheheightandthicknessofthefin.Aswithplanardevices,thedrawngatelength(notshown)separatingthesourceanddrainnodesisa“criticaldesigndimension”.Aswillbedescribed
4、inthenextinstallmentinthisseries,theh_finandt_finmeasuresaredefinedbythefabricationprocess,andarenotdesignparameters.flObulksiliconsubstrateFigure1.FinFETcross-section,withgatedielectriconfinsidewallsandtop,andbulksiliconsubstrateTheFinFETcross-sectiondepictsthegatespanningbothsidesandthetopofthefin
5、.Forusedtorealizeansimplicity,asinglegatedielectriclayerisshown,abstractingthecomplexmulti-layerdielectricsusedtorealizean“effective”oxidethickness(EOT).Similarly,asimplegatelayerisshown,abstractingthemultiplematerialscomprisingthe(metal)gate.Intheresearchliterature,FinFETshavealsobeenfabricatedwith
6、athickdielectriclayerontop,limitingthegateselectrostaticcontrolonthefinsilicontojustthesidewalls.Someresearchershaveevenfabricatedindependentgatesignals,oneforeachfinsidewall-inthiscase,onegateisthedeviceinputandtheotherprovidestheequivalentofFET“backbiascontrol.Fortheremainderofthisseries,thediscus
7、sionwillfocusonthegateconfigurationshown,withathingatedielectriconthreesides.(Inteldenotesthisas-Gate”inllnieirrecentIvyBridgeproductannouncements.)Duetothemorecomplexfabricationsteps(andcosts)of-gate”ualand“independent-gate”devices,theexpectationisthatthesealternativeswillnotreachhighvolumeproducti
8、on,despitesomeoftheiruniqueelectricalcharacteristics.AnotherfabricationalternativeistoprovideanSOIsubstrateforthefin,ratherthanthebulksiliconsubstrateshowninthefigure.Inthisseries,thefocuswillbeonbulkFinFETs,althoughdifferencesbetweenbulkandSOIsubstratefabricationwillbehighlightedinseveralexamples.F
9、igure2.Multiplefinsinparallelspaceds_finapart,commongateinputFigure2illustratesacross-sectionofmultiplefinsconnectedinparallel,withacontinuousgatematerialspanningthefins.TheSourceandDrainnodesoftheparallelfinsarenotvisibleinthiscross-sectionsubsequentfigureswillshowthelayoutandcross-sectionviewofpar
10、allelS/Dconnections.Theuseofparallelfinstoprovidehigherdrivecurrentintroducesathirdparameter,thelocalfinspacing(s_fin).Simplistically,theeffectivedevicewidthofasinglefinis:(2*h_fin+t_fin),thetotalmeasureofthegateselectrostaticcontroloverthesiliconchannel.Thegoalofthefabricationprocesswouldbetoenable
11、asmallfinspacing,sothattheFinFETexceedsthedevicewidththataplanarFETprocesswouldotherwiseprovide:s_fin(2*h_fin+t_fin)SubsequentdiscussionsinthisserieswillreviewsomeoftheuniquecharacteristicsofFinFETs,whichresultinbehaviorthatdiffersfromthesimple(2*h+t)channelsurfacecurrentwidthmultiplier.Theidealtopo
12、logyofa“tall,narrow”finforoptimumcircuitdensityismitigatedbythedifficultiesandvariationsassociatedwithfabricatingahighaspectratiofin.Inpractice,anaspectratioof(h_fin/t_fin2:1)ismorerealistic.OneimmediateconsequenceofFinFETcircuitdesignisthattheincrementsofdevicewidtharelimitedto(2h+t),byaddinganothe
13、rfininparallel.Actually,duetotheuniquemeansbywhichfinsarepatterned,acommondevicewidthincrementwillbe(2*(2h+t),aswillbediscussedinthenextinstallmentinthisseries.ThequantizationofdevicewidthinFinFETcircuitdesignisdefinitelydifferentthanthecontinuousvaluesavailablewithplanartechnology.However,mostlogic
14、cellsalreadyuselimiteddevicewidthsanyway,andcustomcircuitoptimizationalgorithmstypicallysupport“snapping”toafixedsetofavailablewidthvalues.SRAMarraysandanalogcircuitsarethemostimpactedbythequantizedwidthsofFinFETs-especiallySRAMbitcells,wherehighlayoutdensityandrobustreadability/writeabilitycriteria
15、bothneedtobesatisfied.Theunderlyingbulksiliconsubstratefromwhichthefinisfabricatedistypicallyundoped(i.e.,averylowimpurityconcentrationpercm*3).TheswitchinginputthresholdvoltageoftheFinFETdevice(Vt)issetbytheworkfunctionpotentialdifferencesbetweenthegate,dielectric,and(undoped)siliconmaterials.Altho
16、ughthesiliconfinimpurityconcentrationiseffectivelyundoped,theprocessneedstointroduceimpuritiesunderthefinasachannelstop,toblock“punchthrough”currentbetweensourceanddrainnodesfromcarriersnotcontrolledelectrostaticallybythegateinput.Theoptimummeansofintroducingthepunchthrough-stopimpurityregionbelowth
17、efin,withoutsubstantiallyperturbingthe(undoped)concentrationinthefinvolumeitself,isanactiveareaofprocessdevelopment.ModernchipdesignsexpecttohavemultipleVtdeviceofferingsavailable-e.g.,a“standard”Vt,a“high”Vt,anda“lowto”enVatble-cell-swapoptimizationsthattrade-offperformanceversus(leakage)power.Fore
18、xample,thedelayofanSVT-basedlogiccircuitpathcouldbeimprovedbyselectivelyintroducingLVT-basedcells,attheexpenseofhigherpower.Inplanarfabricationtechnologies,multipleVtdeviceofferingsarereadilyavailable,usingasetofthreshold-adjustingimpurityimplantsintomaskedchannelregions.InFinFETtechnologies,differe
19、ntdevicethresholdswouldbeprovidedbyanalternativegatemetallurgy,withdifferentworkfunctionpotentials.Theavailabilityofmultiple(nFETandpFET)devicethresholdsisagoodexampleofthetradeoffsbetweenFinFETsandplanardevices.Inaplanartechnology,thecostofadditionalthresholdofferingsisrelativelylow,asthecostofanad
20、ditionalmaskingstepandimplantisstraightforward.However,themanufacturingvariationinplanardeviceVtsdueto“channelrandomdopantfluctuation(RDF)fromtheimplantsishigh.ForFinFETs,thecostofadditionalgatemetallurgyprocessingformultipleVtsishigher-yet,noimpurityintroductionintothechannelisrequired,andthus,litt
21、leRDF-basedvariationismeasured.(Cost,performanee,andstatisticalvariationcomparisonswillcomeuponseveraloccasionsinthisseriesofarticles.)Thelowimpurityconcentrationinthefinalsoresultsinlesschannelscatteringwhenthedeviceisactive,improvingthecarriermobilityanddevicecurrent.Conversely,FinFETsintroduceoth
22、ersourcesofvariation,notpresentwithplanardevices.Thefinedge“roughness”willresultinvariationindeviceVtanddrivecurrent.(Chemicaletchstepsthatareselectivetothespecificsiliconcrystalsurfaceorientationofthefinsidewallareusedtohelpreduceroughness.)ThecharacteristicsofbothplanarandFinFETdevicesdependuponGa
23、teEdgeRoughness,aswell.ThefabricationofthegatetraversingthetopologyoverandbetweenfinswillincreasetheGERvariationforFinFETdevices,asshowninFigure3.Figure3.SEMcross-sectionofmultiplefins.Gateedgeroughnessoverthefinishighlightedintheexpandedinsetpicture.FromBaravelli,etal,ImpactofLineEdgeRoughnessandRa
24、ndomDopantFluctuationonFinFETMatchingPerformanee”,IEEETransactionsonNanotechnology,v.7(3),May2008.ThenextentryinthisserieswilldiscusssomeoftheuniquefabricationstepsforFinFETs,andIntroductiontohowthesestepsinflueneedesign,layout,andDesignforManufacturability:FinFETtechnologyPartIIThemajorprocesssteps
25、infabricatingsiliconfinsareshowninFigures1through3.ThestepthatdefinesthefinthicknessusesSidewallImageTransfer(SIT).Low-pressurechemicalvapor(isotropic)depositionprovidesauniquedielectricprofileonthesidewallsofthesacrificialpatternedline.Asubsequent(anisotropic)etchofthedielectricretainsthesidewallma
26、terial(Figure1).Reactiveionetchingofthesacrificiallineandtheexposedsubstrateresultsinsiliconpedestals(Figure2).Depositionofadielectrictocompletelyfillthevolumebetweenpedestalsisfollowedbyacontrolledetch-backtoexposethefins(Figure3).deposrtedCVDdielectncsacrificialSfTpatternS!Tsidewallsafteranisotrop
27、icEtchSisubstrateFigure1.Cross-sectionofsidewallsonsacrificiallinesafterCVDetch.SisubstrateJSipedestalsafterRIEetchofsiliconusingSITFigure2.Cross-sectionofsiliconpedestalsafterRIEetch,usingSidewallImageTransfergateFigure3.Cross-sectionofsiliconfinsafteroxidedepositonandetch-back,andgatedepositon.sil
28、ieonfinsafteroxidedepositionandetch-back(gateoxideonfinnotshown)fieldoxideLow-pressuredielectricdepositiontocreatesidewallsonapolysiliconlineisawell-knowntechnique-itiscommonlyusedtoseparate(deep)source/drainimplantareasfromtheplanarFETtransistorchannel.FinFETfabricationextendsthistechniquetopattern
29、definitionforsiliconfinetching.ThereisnophotolithographystepassociatedwithSIT,justthepatterningofthesacrificiallines.Asaresult,thefinthicknesscanbesmallerthanthephotolithographicminimumdimensions.Thefinthicknessisdefinedbywell-controlleddielectricdepositionandetchingstepsratherthanphotoresistpattern
30、ing,reducingthemanufacturingvariation.However,thereisvariationinfinheight,resultingfrom(local)variationsintheetch-backrateofdielectricremoval.(ForFinFETsonanSOIsubstrate,thefinheightisdefinedbythesiliconlayerthickness,withanaturalsiliconetch-stopattheinsulatorinterfaceincontrasttothetimed-etchfinhei
31、ghtforbulksubstratepedestals.)ThereareseveralcharacteristicstonoteaboutSITtechnology.Nominally,finscomeinpairsfromthetwosidewallsofthesacrificialline.Addingfinsinparalleltoincreasedrivecurrenttypicallyinvolvesaddingapairoffins:delta_w=(2*(2*h_fin+t_fin).To“cut”fins,amaskedsiliconetchingstepisrequire
32、d.Therearetwoconsiderationsforcuttingfins.Thefirstinvolvesbreakinglongfinsintoindividualpairs.Theotheristocreateanisolatedfin,byremovingitsSIT-generatedneighbor.Criticalcircuitsthatrequirehighdensityand/ordifferentdevicesizingratiosmayjustifytheneedforisolatedfinpatterning-e.g.,SRAMbitcells.Compared
33、tocutting,isolatedfinpatterningmayinvolvedifferentdesignrulesandseparate(critical)lithographysteps,andthusadditionalcosts.Additionalprocessstepsarerequiredtointroduceimpuritiesoftheappropriatetypebelowthefintoprovideapunchthroughstop(PTS),ensuringthereisnodirectcurrentpathbetweendrainandsourcethatis
34、notelectrostaticallycontrolledbythegateinput.Thedielectricbetweenpedestalsthatremainsafteretch-backservesasthefieldoxide,asdenotedinFigure3.Thegatematerialtraversingbetweenparallelfinsiswell-separatedfromthesubstrate,minimizingtheCgxparasiticcapacitance.Theuniformityandcontrolofthefinalfindimensions
35、areimportantprocesscharacteristics,forboththefinthicknessandfincornerprofiles.(Theprofileofthepedestalbelowthefinislesscritical,andmaybequitetapered,asshowninFigure3.)Tolerancesinthefinthicknessarisefromvariationsinthevertical,anisotropicSITsiliconetch.Thefinthicknessatthebottomisalsodependentuponth
36、euniformityoftheetch-backthegoalistominimizeanydielectric“foot”remainingatthebottomofthefin.Aswillbediscussedinthenextseriesinstallment,variationsint_finhavesignificantimpactuponthetransistormodel.Thetopcornerprofilesalsohaveanimpactuponthetransistorbehavior,astheelectricfieldsfromthegatetothesilico
37、nfinareconcentratedinthisregion,originatingfromboththesidewallandtopgatematerials.Gatepatterningfollowsconventionalphotolithographicsteps,althoughtherecentintroductionofmetalgatematerialshascertainlyaddedtothecomplexity,especiallyasthegatemustnowtraverseconformallyoverparallelfins.AswithaplanarFETte
38、chnology,thegatelengthisthecriticaldimensionthatistypicallyquotedasthebasisfortheprocessnode-e.g.,20nm.IncontrasttoplanarFETtechnologies,providingmultipleFinFETthresholdvoltage(Vt)offeringsrequiressignificantadditionalprocessengineering.ThethresholdofanyFETisafunctionoftheworkfunctionpotentialdiffer
39、encesbetweenthegate,dielectric,andsiliconsubstrateinterfaces.InplanarFETs,multipleVtofferingsarereadilyprovidedbyshallow(masked)impurityimplantsintothesubstratepriortogatedeposition,adjustingtheworkfunctionpotentialbetweendielectricandchannel.However,thevariationinthe(verysmall)dosageofimpuritiesint
40、roducedintheplanarchannelresultsinsignificantVtvariation,duetorandomdopantfluctuation(RDF).WithFinFETs,thereisongoingprocessdevelopmenttoprovidedifferentmetalgatecompositions(andthus,metal-to-dielectricworkfunctions)asthepreferredmethodforVtadjust.Theadvantageofusingmultiplegatemetalswillbetoreducet
41、heRDFsourceofVtvariationsubstantially,ascomparedtoimplantinga(very,verysmall)impuritydosageintothefinvolume.Thedisadvantageistheadditionalprocesscomplexityandcostofprovidingmultiplemetalgatecompositions.AnotherkeyFinFETprocesstechnologydevelopmentisthefabricationofthesource/drainregions.Aswasmention
42、edinthefirstseriesinstallment,thesiliconfiniseffectivelyundoped.Althoughadvantageousforthedevicecharacteristics,theundopedfinresultsinhighseriesresistanceoutsidethetransistorchannel,whichwouldotherwisenegatethedrivecurrentbenefitsoftheFinFETtopology.ToreducetheRsandRdparasitics,aspaceroxideisdeposit
43、edontheFinFETgatesidewalls,inthesamemannerassidewallswerepatternedearlierforSITfinetching.Toincreasethevolumeofthesource/drain,asiliconepitaxygrowth(SEG)stepisused.TheexposedS/Dregionsoftheoriginalfinserveasthe“seed”forepitaxialgrowth,separatedfromtheFinFETgatebythesidewallspacer.Figure4showsthesour
44、ce/draincross-sectionaftertheSEGstep.CurrentDensity(Afcm2)1E6E5IJsilicideFigure4.Crosssectionofsource/drainregion,afterepitaxialgrowth.Originalfinisinblue-notethefacetedgrowthvolume.ThecurrentdensityintheS/Dpastthedevicechanneltothesilicidetopisverynon-uniform.FromKawasaki,etal,IEDM2009,p.289-292.Theincorporationofimpuritiesoftheappropriatetype(fornFETorpFET)duringepitaxialgrowthreducestheS/Dresistivitytoamoretolerablelevel.Theresistivityisfurtherredu
温馨提示
- 1. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。图纸软件为CAD,CAXA,PROE,UG,SolidWorks等.压缩文件请下载最新的WinRAR软件解压。
- 2. 本站的文档不包含任何第三方提供的附件图纸等,如果需要附件,请联系上传者。文件的所有权益归上传用户所有。
- 3. 本站RAR压缩包中若带图纸,网页内容里面会有图纸预览,若没有图纸预览就没有图纸。
- 4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
- 5. 人人文库网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对用户上传分享的文档内容本身不做任何修改或编辑,并不能对任何下载内容负责。
- 6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
- 7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
最新文档
- 2025年贵阳市息烽县(中小学、幼儿园)教师招聘试题及答案
- 农药残留清除剂在农业生产模式变革中的应用前景考核试卷
- 区域家用纺织品市场区域市场品牌忠诚度培养策略分析考核试卷
- 劳务派遣行业可持续发展策略研究考核试卷
- 工业产品检测中的3D打印动态性能模拟考核试卷
- 2025教师编制考试必考面试题库及答案
- 信息系统安全监督与评估持续改进机制创新考核试卷
- 音阶调整教程考核试卷
- 体育会展产业链整合与创新考核试卷
- 团队协作在医疗器械企业研发流程中的作用考核试卷
- 柴油车排气后处理装置技术要求 第2部分:选择性催化还原转器( SCR )(T-CAEPI 12.2-2017)
- 《呼吸门诊综合诊疗室设置与管理规范》编制说明
- 希沃一体机技术方案
- 学生床上用品采购投标方案
- 2023年08月湖北黄冈市直事业单位引进高层次人才116人笔试历年高频考点试题含答案带详解
- 铝箔常见缺陷
- 幼儿园教师的专业发展路径
- 护理学导论(第二版)高职PPT完整全套教学课件
- 2021年06月江苏泰州市兴化市农村订单定向医学生免费培养宣传材料笔试参考题库含答案解析
- 金属非金属矿山重大生产安全事故隐患判定标准课件
- 电力公司220千伏及以上电网建设项目档案管理实施
评论
0/150
提交评论