第九章 同步状态机课件

1、2022-5-112022-5-122022-5-132022-5-142022-5-152022-5-16StateNext_Statein/outin/out2022-5-172022-5-182022-5-19GF2022-5-110GF2022-5-1112022-5-1122022-5-113Idle Start Stop Clear A/G=0 !A A/F=1 !Reset /F=0 G=0!Reset /F=0 G=0 !Reset | !A/F=0 G=1 状态转移图!Reset /F=0 G=02022-5-1142022-5-1152022-5-1162022-5-117

2、例12022-5-1182022-5-1192022-5-120例22022-5-1212022-5-1222022-5-123module fsm (Clock, Reset, A, F, G);input Clock, Reset, A;output F,G;reg 1:0 state, Nextstate;parameter Idle = 2b00, Start = 2b01, Stop = 2b10, Clear = 2b11;always (posedge Clock) begin if (!Reset) begin state = Idle; end else state = Ne

3、xtstate; end2022-5-124always ( state or A ) begin F=0; G=0; if (state = Idle) begin if (A) Nextstate = Start; else begin Nextstate = Idle; G=1; end end else if (state = Start) if (!A) Nextstate = Stop; else Nextstate = Start;else if (state = Stop) if (A) Nextstate = Clear; else Nextstate = Stop; els

4、e if (state = Clear) begin if (!A) Nextstate = Idle; else Nextstate = Clear; F=1; end else Nextstate= Idle; endendmodule 黄色是我加的，怀疑老师写错了例32022-5-1252022-5-1262022-5-127assign G=state3;assign F=state0;parameter /- G_ i_ j_ F-/ Zero=4b0_0_0_0, Idle=4b0_0_0_0, start=4b0_0_0_0, stop=4b0_0_0_0, clear=4b0_0_0_0,例42022-5-1282022-5-1292022-5-1302022-5-1312022-5-1322022-5-1332022-5-1342022-5-1352022-5-1362022-5-1372022-5-1382022-5-1392022-5-1402022-5-1412022-5-1422022-5-1432022-5-1442022-5-1452022-5-146always (posedge clk) begin if(reset) begin /*置输出为置输出为0*/ end else if