WAT-电性参数介绍(WAT-Parameters-introduction)

1、WAT-电性参数介绍(WAT-Parameters-introduction)2WAT Parameters ReviewSpeaker: Alan Huang3FlowWhy WAT?WAT Parameter Review.Process test Methodology.Device test Methodology.Process Factor Influence on WAT Para.WAT ApplicationGeneral Guide-line when WAT failExle introduce4 Why WAT?Debug the Process Error. Moni

2、tor Process Window.Check Design Rule.Control the Process Parameters(SPC).Reliability Characterization.Device Modeling for Circuit Design.Develop next Generation.5(in=13206.24614.8)TST2TST1TST7TST3TST4TST8TST9TST5TST6(out=13326.24734.8)(0.0)frame=120 x120Test site and Test line location6 Device Categ

3、orizationActive Device MOSFET(N/P),Field Transistor,BJT,DiodePassive Device Resistor,CapacitorsDesign rules Isolation,lines(Spacing,Continuity) contact,extensionResistorDiffusion regions N+,N-,P+,N-Well,P-Well,Deep-NWThin films P1,P2,M1,M2,M3Contact: C3 to N+/P+,Via C3 to P1,P27WAT Parameter ReviewP

4、rocess Part:Spacing (Bridge,short)Continuity (Open)IsolationSheet RsContact RcKelvin Structure for ResistanceIntegrity (Inter layer dielectric)Extension rule checkCD measurement1)Junction leakageDevice Part:Gm (Vth,Current Gain)Idsat (Asym)IoffSwingGamma factorBKVIsubLeff,Rext,WeffField Device test1

5、)Capacitance8Process Part:(1) Spacing (Bridge,short)Define：验证在Process中，同层/同层之间的隔绝能力!Measurement method：Force 1uA电流到导线上，假若线路中有short，则测量出的电压值就偏低(50的结构中, Force I=0.01uA and Voltage lim=10V!(Req=L/W) Pad1Pad2Pad3Pad41um15um70um2um(W)70um1000L14Process Part:(7) Integrity(Gate-Oxide-Integrity)Define:验证Gat

6、e oxide 的Quality 好坏之一项参数当Gate oxide uniformity不均,或Interface间有defects时,会形成一漏电流路径失去Oxide Isolation的能力！Measurement method:一般测量法不外乎Force V/I and measure I/V1. Force V and measure I: Sweep Volt on Poly gate,and Vb=ground then measure Ig(aboutpA),If Ig increase to 1uA,this Sweep Volt is BKV(normal large 7

7、 V)2. Force I and measure V: Force 1uA on Poly gate then measure VoltagePS:测量方式取决于Pattern design (common pad issue)WELLPoly Gate15Process Part:(8) Extension rule checkDefine：以sense漏电流的方式，测量Contact overlay 的Design rule check!PS：(1) 一般来说，layout 的结构会采用十字架的形式，最大的好处是在把shot issues 的问题抓出! (2) miss-align 与c

8、ontact number无关！M2ViaM1M1 ext to via用Poly4垫16Process Part: (9) CD measurementDefine: 籍由测量两条同长度，不同宽度的电阻，换算出其宽度CD大小！PS: 当W=W1时 可测量得电阻R1 W=W2时 可测量得电阻R2 R1=Rs*L/(W1-W)R2=Rs*L/(W2- W)R1/R2=(W2- W) /(W1-W)则W(CD loss),Rs皆可求得！ (P1 CD 大小影响到Channel length的长短,需特别注意）17Process Part:(10) Junction leakageDefine：一般

9、来说leakage指的是反向偏压时的漏电流测量，通常有以下三种分类： 1.Contact leak 2.Dielectric leak (usually for DRAM)3.Junction leak (bulk or peri)PS: I-bulk(meas)=A-bulk*J-area(current/um2)+L-peri*J-peri(current/um) I-finger(meas)=A-fing*J-area(current/um2)+L-peri(current/um) (J-area,J-peri 可求）PW拉出NAA有打Blanket N+impN-impC3M118De

10、vice Part:Gm (Vth,Current Gain)Define:Gm=(Id/ Vg)Linear:Id=1/2(CoxW/L)(2(Vgs-Vt)Vds-Vds2)Gm= CoxW/L Saturation:Id=1/2(CoxW/L)(Vgs-Vt)2Gm= CoxW/L(Vgs-Vt)Pinch-Off:Vds=Vgs-VtGm= Cox(W/L)Vds= Cox(W/L)PS:If value abnormal,It may have Gox, Leff or implant issues.Vth Measure method:Step1:Vds=0.1 Vs=Vb=0 a

11、nd swoop VgStep2:Plot Ids Vgs and Gm Vgs curvesStep3:find Gm(max),plot slop of this point on Ids VgsFrom Linear function set Id=0then Vth=Vgs-V03VgId19Device Part:Idsat (Asym)Define: Idsat=Ids at Vgs=Vds=VccIds Measure method:Step1:Vs=Vb=0,Vd=Vcc and Sweep VgStep2:Plot Ids VgsStep3:Find Ids at Vg=Vd

12、=VccIds Asymmetry check:Step1:Following the Ids measurement.Step2:Change Drain and Source Pin-assign,then measure Ids.Step3:Asym=ABS(Ids-Ids)/IdsPS:If Ids Asymmetry Avnormal, It may have the Isub,(or Poly gate non-overlap issues)or LDD N-Rs, or Contact Rc some things trouble!ASMU2VgGDSSubVsubSMU3IdV

13、dSMU120Device Part:IoffDefine: Ids=Ioff at Vgs=Vs=Vb=0,Vds=VccIoff Measure method (Direct meas.):Step1:Vs=Vb=0,Vd=Vcc and Sweep VgStep2:Plot Ids VgsStop3:Find Ids at Vg=0Ps: 测量机台的灵敏度，须注意与曲线的相 关联性！Ioff Measure method (外插法外插法):Step1:Follow the Ioff Direct meas.methodStep2:Plot Max slop of this curve o

14、n log(Ids) VgsStep3:Find the Ids at Vg=0 intercept.logIdVgVd=VcclogIdVgVd=Vcc21Device Part:Swing (Subthreshold Slop,St)Define:Swing=(log(Ids)/ Vgs)-1=2(kt/q)(1+Cd/Cox)*当Vg逐渐增加,channel accumulationdeplationweak inversionstrong inversion,Swing既是测量weak inversion时Id与Vg的变化程度!(exponential)DIBl effect meas

15、urement:Step1:Vs=Vb=,Vd= and Sweep VgStep2:Plot log(Ids) VgsStep3:Plot Max slop of this curve on log(Ids) VgsStep4:Repeat (a) but Vd=VccStep5:Repeat (b),PS:如果发生punch-through (Subsurface-DIBL),High drain St will larger than Low drain. (Swing越大 ,Leakage越大 )01VDS=5VVDS=0.1VVGID22Device Part:Gamma facto

16、rDefine:=(2qNa1/2/Cox=Vt/(2f+Vbs1)1/2 -(2f+Vbs2) 1/2) Vt=Vf+2f+(2qNb(2f+Vsb)1/2/Cox*Gamma factor是在计算Substrate与Source间非等电位时，对Vt变化的影响.(Vt值需依Vbs的大小改变来计算)Measurement method:Step1:Fixed Vd=VStep2:Measure Vt under various Substate bias.Step3:Plot Vt versus(2f+Vbs)1/2 curveStep4:slope of the curve is taken

17、 to be Gammar factor.PS:Vt adjusment, Deep implant, well implant, well implant都会影响此一参数，通常Vt浓度越高，值越大!同理，不同的device在相同的Back-bias测量下，Vt差值，亦代表着值的影响VDVGN2N123Device Part:BKVDefine:Drain voltage which produces 1uA Drain Current.Breakdown Voltage是用来 test MOS的耐压程度。(1) 在Long channel的Device，看的是S/D to well 间jun

18、ction的崩溃电压(2) 在Short channel的status，看到的BKV，有可 能是来自drain to source因punch-through造成 的低电压现象!PS:可籍由Id流到Is or Ib来判断BKV由何种造成！Measurement method:Step1:Vs=Vg=Vb=VStep2:set up Drain current limited at 1uA.Step3:Plot Ids VdsStep4:Sweep Vd and find the Voltage at Id =1uAN+N+VSVGVDVB24Device Part:IsubDefine:Isu

19、b (Measure MOS hot carrier effect.)Isub=f( Vds,Vgs)(1)Vds 对Isub impact:Pinch off point VDsat=Vgs VtIf Vds,VD-Vdsat then Emax,Isub(2)Vgs对Isub impact:一开始Vgs,Id then Isub,但当过pinch off point时 Vgs ,VD-Vdsat,then Emax IsubMeasurement method:Step1:Vs=Vb=0V,and Vd=VccStep2:Sweep Vg (Vgmin1/2Vd)Step3:Plot Is

20、ub VgsStep4:Isub=IsubmaxPS:If Isub abnormal, it may cause from hot carrier, Poly gate non-overlap,Contact over etchingand so on.AVgGDSSubIsubSMU3IdVdSMU2SMU1AVsubMeasurement Circuit0Method, CharacteristicsIsubVgPeak PointVg limit=Vd25Device Part:Leff,Weff and RextDefine: Leff=Lmask-2L,Rext=Rm- Rchan

21、nel,Weff=Wmask-2 W公式推导：公式推导：IDS=(Weff/Leff)*Cox*n*(Vgs-Vt-0.5VDS )VDSRch=VDS/IDS=Leff/(Weff*Cox*n*(Vgs-Vt-0.5VDS)Rm=Vf/Im=Rext+Rch=Rext+A(Lmask-2L)A=1/(Weff *Cox*n*(Vgs-Vt-0.5VDS)Measurement method:Step1:Fixed VDS=0.1V,Vb=Vs=0VStep2:变化Vgs-Vt=2,3VStep3:Plot Rm LmaskStep4:选相同的Channel Width不同的length的de

22、vice测量不同的 Vgs-Vt Bias 下的IDS,计算Rm=VDS/IDSStep5:计算两直线交点 X轴截距=2 L (2W 算法同） Y轴截距=Rext 01432567Rext=1650100150200VDS=0.1VVgS=0VGS=6VVGS=8VVGS=10VVGS=12VVGS=14V26Device Part:Field Device testDefine:测量Active region与field oxide 所 形成的寄生元件之Isolation能力测 试！考虑不同的 layout结构，有以下两种测量法：Measurement method:Field Oxide上

23、有导电材料覆盖： 此结构如同一AMOS元件，MOS Vt的大小，即反映出Field Isolation能力的好坏！ PS: 测量方法同Vth测量法！(2) Field oxide 上无导电材料覆盖： 此结构考虑Acitve range 间implant浓度的Isolation能力，一般是测量Constant current(1uA)下的耐压度 PolyAAFOX27Device Part:Capacitance (thickness meas)Define:电容的结构常见的有一般介质电 容与MOS电容两大类，差别在参 考极板的组成成分！Measurement method: (HP4284)(

24、1) For 一般介质电容： Force Voltage的极性与电容大小无关！(2) for MOS电容： Gox电容的测量方面，要避免空乏层 电容的形成，才能算出Thickness Poly on PW:加负压于Poly gate 上,PW 接地！ Poly on NW:加正压于Poly gate 上,NW 接地！28Process Factor influence on WAT ParaThreshold Voltage (Vt=VFB+/-(2F+QBO/COX)QBO=(2qNB(2F+VSB)1/2(1) NB(Well and Sub Con.),QBO,Vt(2) Gate Ox

25、ide (a)Thickness:tox,COX,Vt (b)Quality:Qfc,Vt(VFB= ms-Qfc/COX)(3) Vt adjust (Vt imp,deep-imp.)(4) Poly1 CD(Leff),QBO,Vt(for short channel)(5) S/D implant,Vt(For short channel)29Process Factor influence on WAT ParaGain factor:=COX(W/L)Mobility ,Id a)GOX/Si interface quality,mobility,current Gain b)Cannel implant Dose,mobility,current GainP1 CD,L,current GainGOX