铝栅+硅栅器件的版图

1、12GateSourceDrain34 以以SiO2为栅介质时，叫为栅介质时，叫MOS器件器件，这，这是最常使用的器件形式。历史上也出现是最常使用的器件形式。历史上也出现过以过以Al2O3为栅介质的为栅介质的MAS器件器件和以和以 Si3N4为栅介质的为栅介质的MNS 器件，以及以器件，以及以SiO2+Si3N4为栅介质的为栅介质的MNOS器件，统称器件，统称为金属为金属-绝缘栅绝缘栅-半导体器件半导体器件-MIS 器件。器件。 以以Al为栅电极时，称为栅电极时，称铝栅器件铝栅器件。以重。以重掺杂多晶硅掺杂多晶硅(Poly-Si) 为栅电极时，为栅电极时， 称称硅栅器件硅栅器件。它是当前。它是

2、当前MOS器件的主流器件的主流器件。器件。5 硅栅工艺硅栅工艺是利用重掺杂的多晶硅来代替是利用重掺杂的多晶硅来代替铝做为铝做为MOS管的栅电极，使管的栅电极，使MOS电路特性电路特性得到很大改善，它使得到很大改善，它使|VTP|下降下降1.1V，也容，也容易获得合适的易获得合适的VTN值并能提高开关速度和集值并能提高开关速度和集成度。硅栅工艺具有自对准作用，这是由成度。硅栅工艺具有自对准作用，这是由于硅具有耐高温的性质。栅电极，更确切于硅具有耐高温的性质。栅电极，更确切的说是在栅电极下面的介质层，是限定源、的说是在栅电极下面的介质层，是限定源、漏扩散区边界的扩散掩膜，使栅区与源、漏扩散区边界的

3、扩散掩膜，使栅区与源、漏交迭的密勒电容大大减小，也使其它寄漏交迭的密勒电容大大减小，也使其它寄生电容减小，使器件的频率特性得到提高。生电容减小，使器件的频率特性得到提高。另外，在源、漏扩散之前进行栅氧化，也另外，在源、漏扩散之前进行栅氧化，也意味着可得到浅结。意味着可得到浅结。 6 铝栅工艺铝栅工艺为了保证栅金属与漏极铝引线之间为了保证栅金属与漏极铝引线之间有一定的间隔，要求漏扩散区面积要大些。而有一定的间隔，要求漏扩散区面积要大些。而在硅栅工艺中覆盖源漏极的铝引线可重迭到栅在硅栅工艺中覆盖源漏极的铝引线可重迭到栅区，这是因为有一绝缘层将栅区与源漏极引线区，这是因为有一绝缘层将栅区与源漏极引线

4、隔开，从而可使结面积减少隔开，从而可使结面积减少30%40%。硅栅。硅栅工艺还可提高集成度，这不仅是因为扩散自对工艺还可提高集成度，这不仅是因为扩散自对准作用可使单元面积大为缩小，而且因为硅栅准作用可使单元面积大为缩小，而且因为硅栅工艺可以使用工艺可以使用“二层半布线二层半布线”即一层铝布线，即一层铝布线，一层重掺杂多晶硅布线，一层重掺杂的扩散层一层重掺杂多晶硅布线，一层重掺杂的扩散层布线。由于在制作扩散层时，多晶硅要起掩膜布线。由于在制作扩散层时，多晶硅要起掩膜作用，所以扩散层不能与多晶硅层交叉，故称作用，所以扩散层不能与多晶硅层交叉，故称为两层半布线铝栅工艺只有两层布线：一层为两层半布线铝

5、栅工艺只有两层布线：一层铝布线，一层扩散层布线。硅栅工艺由于有两铝布线，一层扩散层布线。硅栅工艺由于有两层半布线，既可使芯片面积比铝栅缩小层半布线，既可使芯片面积比铝栅缩小50%又又可增加布线灵活性。可增加布线灵活性。78光刻光刻1，刻刻N阱掩膜版阱掩膜版9光刻光刻1，刻刻N阱掩膜版阱掩膜版光刻胶光刻胶掩膜版掩膜版10光刻光刻1，刻刻N阱掩膜版阱掩膜版11光刻光刻1，刻刻N阱掩膜版阱掩膜版12N阱阱13光刻光刻2，刻有源区掩膜版，刻有源区掩膜版二氧化硅二氧化硅掩膜版掩膜版N阱阱14光刻光刻2，刻有源区掩膜版，刻有源区掩膜版二氧化硅二氧化硅氮化硅氮化硅掩膜版掩膜版N阱阱15光刻光刻3，刻多晶硅掩

6、膜版，刻多晶硅掩膜版FOXN阱阱16光刻光刻3，刻多晶硅掩膜版，刻多晶硅掩膜版栅氧栅氧N阱阱17光刻光刻3，刻多晶硅掩膜版，刻多晶硅掩膜版N阱阱18光刻光刻3，刻多晶硅掩膜版，刻多晶硅掩膜版掩膜版掩膜版N阱阱19光刻光刻3，刻多晶硅掩膜版，刻多晶硅掩膜版多晶硅多晶硅N阱阱场氧化层场氧化层栅氧化层栅氧化层20光刻光刻4，刻，刻P+离子注入离子注入掩膜版掩膜版掩膜版掩膜版P+N阱阱21光刻光刻5，刻，刻N+离子注入离子注入掩膜版掩膜版N+N阱阱22PSGN阱阱23光刻光刻6，刻接触孔刻接触孔掩膜版掩膜版P+N+N阱阱24光刻光刻7，刻刻Al掩膜版掩膜版AlN阱阱25VDDVoVSSN阱阱26光刻光

7、刻8，刻压焊孔刻压焊孔掩膜版掩膜版钝化层钝化层N阱阱27 Step 0: Start with a bare n-type silicon wafer.N Doped Silicon28 *Step 1: (layering) Grow thick layer (5000) of silicon dioxide (field oxide) to act as a doping barrier.N Doped SiliconThick Field Oxide29 *Step 2a: (patterning) Apply photoresist.N Doped SiliconThick Field

8、 OxidePhotoresist30 Source/Drain: Photomask (dark field) mask 1 Clear GlassChromiumCross Section31 Step 2b: (patterning) Expose photoresist to create temporary pattern for source/drain regions.N Doped SiliconThick Field OxidePhotoresistUltraviolet LightPhotomask32 Step 2c: (patterning) Develop photo

9、resist, completing temporary pattern for source/drain regions.N Doped SiliconThick Field OxidePhotoresist33 Step 2d: (patterning) Wet etch permanent openings for source/drain into field oxide.N Doped SiliconThick Field OxidePhotoresist34 Step 2e: (patterning) Remove photoresist. Permanent pattern re

10、mains in the silicon dioxide.N Doped SiliconThick Field Oxide35 Source/Drain Windows: Microscope View mask 1 Bare SiliconThick Field OxideCross Section36 *Step 3a: (doping) Apply p-type spin-on dopant film. Boron penetrates into the silicon through the holes in the field oxide to begin formation of

11、the source and drain regions.N Doped SiliconP+ DrainP+ SourceThick Field OxideBoron-Doped Spin-On Oxide37 Step 3b: (heat treatment) Drive dopants deeper into silicon using high temperatures (1000), completing formation of the source and drain regions.N Doped SiliconP+ DrainP+ SourceThick Field Oxide

12、Boron-Doped Spin-On OxideP+ DrainP+ SourceChannel Length - Leff38 Step 4a: (layering) Wet etch to remove SOD (spin-on dopant) and field oxide layers.N Doped SiliconP+ DrainP+ Source39 Source/Drain Doping: Microscope View Mask1 P+ Doped Source and Drain (not actually visible)N-Doped SubstrateCross Se

13、ction40 *Step 4b: (layering) Regrow new field oxide layer.Thick Field OxideN Doped SiliconP+ DrainP+ SourceOxide grows slightly thicker over doped areas.41 *Step 5a: (patterning) Apply photoresist.Thick Field OxideN Doped SiliconP+ DrainP+ SourcePhotoresist42 Gate: Photomask (dark field) mask2Clear

14、GlassChromiumCross Section43 Step 5b: (patterning) Expose photoresist to create temporary pattern for gate region.Thick Field OxideN Doped SiliconP+ DrainP+ SourcePhotoresistUltraviolet LightPhotomask44 Step 5c: (patterning) Develop photoresist, completing temporary pattern for gate region.Thick Fie

15、ld OxideN Doped SiliconP+ DrainP+ SourcePhotoresist45 Step 5d: (patterning) Wet etch permanent opening for gate region into field oxide.Thick Field OxideN Doped SiliconP+ DrainP+ SourcePhotoresist46 Step 5e: (patterning) Remove photoresist. Permanent pattern remains in the silicon dioxide.Thick Fiel

16、d OxideN Doped SiliconP+ DrainP+ Source47 *Step 6: (layering) Grow thin layer (700) of silicon dioxide to act as the gate oxide for the transistor.Thick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate Oxide48 After Gate Oxide Growth: Microscope ViewP+ Doped Source and Drain (under Field Oxide)T

17、hick Field OxideThin Gate OxideCross Section49 *Step 7a: (patterning) Apply photoresist.Thick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate OxidePhotoresist50 Step 7b: (patterning) Expose photoresist to create temporary pattern for contact holes.Thick Field OxideN Doped SiliconP+ DrainP+ Sour

18、ceThin Gate OxidePhotoresistUltraviolet LightPhotomask51 Contacts: Photomask (dark field) mask 3Clear GlassChromiumCross Section52 Step 7c: (patterning) Develop photoresist, completing temporary pattern for contact holes.Thick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate OxidePhotoresist53 S

19、tep 7d: (patterning) Etch permanent holes for contacts into field oxide.Thick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate OxidePhotoresist54 Step 7e: (patterning) Remove photoresist. Permanent contact holes in the field oxide remain.Thick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate

20、 Oxide55 After Contact Patterning: Microscope ViewContact Hole (bare silicon)P+ Doped Source and Drain (under Field Oxide)Thick Field OxideThin Gate OxideCross Section56 *Step 8a: (layering) Deposit aluminum layer over entire wafer surface.MetalThick Field OxideN Doped SiliconP+ DrainP+ SourceThin G

21、ate Oxide57 Step 8b: (heat treatment) Alloy aluminum at moderate temperatures (450) to form good electrical contact with silicon. MetalThick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate OxideAlloyed Aluminum-Silicon58 *Step 9a: (patterning) Apply photoresist.MetalThick Field OxideN Doped Sil

22、iconP+ DrainP+ SourceThin Gate OxidePhotoresist59 Step 9b: (patterning) Expose resist to create temporary pattern to define metal interconnects and gate electrode.MetalThick Field OxideN Doped SiliconP+ DrainP+ SourceThin Gate OxidePhotoresistUltraviolet LightPhotomask60 Metal Interconnects: Photomask (light field)ChromiumClear GlassCross Section61 Step 9c: (patterning) Develop photoresist, completing temporary pattern for metal interconnects and gate electrode.MetalThick F