EDA程序改错题

1、程序改错题已知sel为STD_LOGIC_VECTORPOWNTO类型的信号，而a、b、c、d、q均为STD_LOGIC类型的信号，请判断下面给出的CASE句程序片段：CASEselISWHEN00”=>q<=a；WHEN01”=>q<=b;WHEN10”=>q<=c；WHEN11”=>q<=d;ENDCASE答案：CAS命句缺“WHENOTHER弟句。1. 已知data_in1,data_in2为STD_LOGIC_VECTOR(15DOWNTO晚型的输入端口，data_out为STD_LOGIC_VECTOR(15DOWNTOW的输出端口，a

2、dd_sub为STD_LOGI缺型的输入端口，请判断下面给出的程序片段：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYaddISPORT(data_in1,data_in2:ININTEGER;data_out:OUTINTEGER;ENDadd;ARCHTECTUREadd_archOFaddISCONSTANTa:INTEGER<=2BEGINdata_out<=(data_in1+data_in2)*a;ENDaddsub_arch;答案：常量声明时赋初值的“<=”符号应改用“：=”符号。2. 已知Q为STD_LOGICt型的

3、输出端口，请判断下面的程序片段：ARCHITECTUREtest_archOFtestISBEGINSIGNALB:STD_LOGICQ<=B;ENDtest_arch答案：信号SIGNAL的声明语句应该放在BEGIN语句之前。3. 已知A和Q均为BIT类型的信号，请判断下面的程序片段：ARCHITECTUREarchtestOFtestISBEGINCASEAISWHEN'0'=>Q<='1'WHEN'1'=>Q<='0'ENDCASEENDarchtest;答案：CAS耶句应该存在于进程PROCE

4、SS。1. 三.判断改错题（3分X6题）（评分标准：给出正确答案1分/题；答案基本正确0.5分/题。）已知简日。均为BIT类型的信号，请判断下面的程序片断：ARCHITECTUREtestOFtestISBEGINCASEAISWHEN'0'=>Q<='1'WHEN'1'=>Q<='0'ENDCASE;ENDtest;【参考答案】：CASE句应该存在于进程PROCESS。已知start为STD_LOGI蒙型的信号，su说INTEGERS型的信号，请判断下面的程序片断：PROCESS（start）BEGINF

5、ORiIN1TO9LOOPsum:=sum+i;ENDLOOP;ENDPROCESS【参考答案】：sum是信号，其赋值符号应该由“：=”改为“<=”。2. 已知6STD_LOGICt型的输出端口，请判断下面的程序片断：ARCHITECTUREtestOFtestISBEGINSIGNALB:STD_LOGIC;Q<=B;ENDtest;【参考答案】：信号SIGNAL勺申明语句应该放在BEGINS句之前。3. 已知闭日B均为STD_LOGI斐型的信号，请判断下面的语句:A<='0'B<='x'【参考答案】：不定态符号应该由小写的x'

6、改为大写的X'。4. 已知A为INTEGER型的信号，B为STD_LOGI0t型的信号，请判断下面的程序片断：ARCHITECTUREtestOFtestISBEGINB<=A;ENDtest;【参考答案】：A和B的数据类型不一致，不能相互赋值。已知sel是STD_LOGIC_VECTORDOWNT0)类型信号，而a、b、c、d、q均为STD_LOGIC类型信号，请判断下面给出的CAS弟句:CASEselISWHEN“00”=>q<=aWHEN“0T=>q<=bWHEN“10”=>q<=cWHEN“1T=>q<=dENDCASE;【

7、参考答案】：CASE句缺"WHENOTHER据句。四、判断下面程序中是否有错误，若有错误请改正;1、SIGNALA,EN:STD_LOGIC;PROCESS(A,EN)VARIABLEB:STD_LOGIC;BEGINIFEN=TTHENB<=A;END;ENDPROCESS;2、RCHITECTUREONEOFSAMPLEISVARIABLEAB,C:INTEGERBEGINC<=A+B;END;五、判断下列程序是否有错误，如有则指出错误所在(10分)程序：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_

8、ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYzyt12ISPORT(R,EN,CP:INbit;Q:BUFFERSTD_LOGIC_VECTOR(0DOWNTO3);CO:OUTSTD_LOGIC);ENDzyt;ARCHITECTUREc10OFzyt12BEGINCO<='1'WHEN(EN='1'ANDQ="1011")ELSE;'0'PROCESS(R,CP)BEGINIFR='1'THENQ<="0000"ELSIF(C

9、P'EVENTANDCP<='1')THENIFEN='0'THENQ<=Q;ELSIFQ="1011"THENQ<='0000'ELSEQ:=Q+1;ENDIF;ENDPROCESS;ENDone;仔细阅读下列程序，回答问题LIBRARYIEEE;-1USEIEEE.STD_LOGIC_1164.ALL;-2ENTITYLED7SEGIS-3PORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);-4CLK:INSTD_LOGIC;-5LED7S:OUTSTD_LOGIC_VECTO

10、R(6DOWNTO0);-6ENDLED7SEG;-7ARCHITECTUREoneOFLED7SEGIS-8SIGNALTMP:STD_LOGIC;-9BEGIN-10SYNC:PROCESS(CLK,A)-11BEGIN-12IFCLK'EVENTANDCLK='1'THEN-13TMP<=A;-14ENDIF;-15ENDPROCESS;-16OUTLED:PROCESS(TMP)-17BEGIN-18CASETMPIS-19WHEN"0000"=>LED7S<="0111111"-20WHEN"

11、0001"=>LED7S<="0000110"-21WHEN"0010"=>LED7S<="1011011"-22WHEN"0011"=>LED7S<="1001111"-23WHEN"0100"=>LED7S<="1100110"-24WHEN"0101"=>LED7S<="1101101"-25WHEN"0110"=>

12、LED7S<="1111101"-26WHEN"0111"=>LED7S<="0000111"-27WHEN"1000"=>LED7S<="1111111"-28WHEN"1001"=>LED7S<="1101111"-29ENDCASE;-30ENDPROCESS;-311. ENDone;-32在程序中存在两处错误，试指出，并说明理由：2. 第14行TMP附值错误第29与30行之间，缺少WHENOTHERS句修

13、改相应行的程序：错误1行号：9程序改为：TMP:STD_LOGIC_VECTOR(3DOWNTO0);错误2行号：29程序改为：该语句后添加WHENOTHERS=>LED7S<="00000001、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT4BISPORT(CLKRSTENA:INSTD_LOGIC;OUTY:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT4B;ARCHITECTUREbehav

14、OFCNT4BISSIGNALCQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,RST,ENA)BEGINIFRST='1'THENCQI<='0000'"0000"ELSIFCLK'EVENTANDCLK='1'THENIFENA="1"THENCQI<=CQI+1;'1'ELSECQI<="0000"ENDIF;ENDIF;OUTY<=CQI;ENDPROCESS;COUT<=CQI(

15、0)ANDCQI(1)ANDCQI(2)ANDCQI(3);ENDbehav;2、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCLK_6DISPORT(CLK,RST:INSTD_LOGIC;CLK_OUT:OUTSTD_LOGIC);ENDCLK_6D;ARCHITECTUREONEOFCLK_6DISVARIABLETEMP:STD_LOGI(SIGNALBEGINPROCESS(CLK)VARIABLECNT6D:INTEGE

16、RRANGE0TO3;CONSTANTSIGN:INTEGER:=2;BEGINIF(RST="1”)THENTEMP<="0”;'1','0'ELSIFCLK'EVENTANDCLK='1'THEN(CLK'EVENTANDCLK=T)IF(CNT6D=SIGN)THENCNT6D:=0;TEMP<=NOTTEMP;ELSECNT6D:=CNT6D+1;ENDIF;ENDIF;ENDPROCESS;CLK_OUT<=TEMP;ENDONE;3、libraryieee;useieee.std_

17、logic_1164.all;entityencoderisport(binstd_logic(7downto0);b:instd_logic_vector(7downto0)y_outstd_logic(2downto0);y:outstd_logic_vector(2downto0)endencoder;architectureoneofencoderisbeginprocess(b)begincasebiswhen"0111111T'=>y<="11T;when"1011111T'=>y<="110"

18、;when"1101111T'=>y<="10T;when"1110111T'=>y<="100"when"1111011T'=>y<="01T;when"1111101T'=>y<="010"when"1111110T'=>y<="00T;when"11111110"=>y<="000"whenothers=>null

19、;endcase;endprocess;endone;4、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcounterISPORT(reset:INSTD_LOGIC;clock:INSTD_LOGIC;num:bufferintegerrange0to3;多一个“；”);END;ARCHITECTUREbehavOFjishuISjishu改为counterBeginProcess(reset,clock)BeginIfreset='1'thennum<=0;Elsifrising_edge(clock)thenIfnum=3

20、thennum<=0;elsenum<=num+1;少endif;endif;endprocess;end;5、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STDLOGICUNSIGNED;STD_LOGIC_UNSIGNED.ALLENTITYLX3_2ISPORT(CLK,CLR,OE:INBIT;D:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDLX3_2;ARCHITECTUREstrucOFLX3_2ISVARIABLEQ_TEMP:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALBEGINPROCESS(CLR)PROCESS(CLK)BEGINIFCLR='0'THENQTEMP<='00000000"00000000"ELSIFCLK='1'THENQ_TEMP<=D;ELS