实验五六报告

1、计算机组织与结构专题实验报告学生专业/班级 陈怡龙 计算机 22 2120505032 电信学院 姜兴宁 2014.11.28学号所在学院指导教师提交日期实验五器的设计和实现一、实验目的学习和掌握器的工作原理及设计方法进一步掌握 VHDL 语言的多层次结构的设计方法和应用二、实验要求1. 完成一个单个2. 完成多个器的设计和调试。器级联的设计和调试。3.进一步掌握 TEC-CA-I 开发板或 XJECA 的 I/O 设备的使用。具体实验要求如下：1. 画出模块的电路图2. 写出模块的 VHDL 程序的结构图（反映出编程者的设计思路）3.分析波形4.设计和调试过程（遇到什么问题及如何解决的？通过

2、截图来比较说明）三、实验内容1利用硬件描述语言 VHDL 设计一个器 SRAM(ROMFIFO 等）；其容量为 64*8bit（若只进行2. 对，容量可以加大）（参阅实验指导书 p131 实验七，例子中增加了 Type/Subtype）。器的所需的各种信号（地址、数据及总线）的实现，有两种方式产生：由时钟发生器模块（另外设计一个读写电路模块）产生 由实验设备 TEC-CA 的开关（量）、按键提供。3. 设计一个时序发生器模块，由它提供给其他模块的时钟信号 clk（后续实验可以利用此功能），其功能：每按一次按钮，产生一个单脉冲（去抖）；具有启动/停止功能（开关）；可以产生连续脉冲信号 clk（周

3、期设为 80ns）（参阅实验指导书 p198 例子及实验五例程）。3. 通过指示灯或4. 利用单片波形观察。（设计）一个更大的器体（字扩或位扩），设计一个读写电路模块（类似 FPGA-CPU）储器进行读写。一个能够运试程序的计算机（参见课内实验一）；对扩充后的存四、设计思路与源代码1. sram 的设计这里设计一个 64x8bit 的 sram，6 位的地址，8 位数据。-wr：写信号（wr 的上升沿写入） rd：读信号-mem.vhd library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;cs：片选信

4、号entity mem isport (address:in std_logic_vector(5 downto 0); data_in:in std_logic_vector(7 downto 0); wr:in std_logic;rd:in std_logic; cs:in std_logic;data_out:out std_logic_vector(7 downto 0);end mem;architecture behave of mem issubtype word is std_logic_vector(7 downto 0); type memory is array(0 t

5、o 63) of word;signal ram:memory; beginwrite_op:process(wr,data_in,address) beginif(wr'event and wr='1') then if(cs='1' and rd='0') thenram(conv_integer(address) <= data_in; end if;end if;end process;read_op:process(cs,rd,ram,address)beginif(cs='1' and rd='1

6、') thendata_out <= ram(conv_integer(address);elsedata_out <= (others=>'Z');end if; end process;end behave;2. 多块 sram 级联只需将上面的 mem 模块进行级联，即可将器字位拓展成128x16bit。address 的最做片选。-memex.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ram isport (address

7、:in std_logic_vector(6 downto 0); data_in:in std_logic_vector(15 downto 0); wr,rd:in std_logic;data_out:out std_logic_vector(15 downto 0);end ram;architecture behave of ram is component mem isport (address:in std_logic_vector(5 downto 0); data_in:in std_logic_vector(7 downto 0); wr:in std_logic;rd:i

8、n std_logic;cs:in std_logic;data_out:out std_logic_vector(7 downto 0);end component;beginmem00:mem port map (address=>address(5 downto 0),data_in=>data_in(7 downto 0), wr=>wr,rd=>rd,cs=>not address(6), data_out=>data_out(7 downto 0);mem01:mem port map (address=>address(5 downto

9、0),data_in=>data_in(15 downto 8), wr=>wr,rd=>rd,cs=>not address(6), data_out=>data_out(15 downto 8);mem10:mem port map(address=>address(5 downto 0),data_in=>data_in(7 downto 0), wr=>wr,rd=>rd, cs=>address(6),data_out=>data_out(7 downto 0);mem11:mem port map (address=

10、>address(5 downto 0),data_in=>data_in(15 downto 8), wr=>wr,rd=>rd, cs=>address(6),data_out=>data_out(15 downto 8);end behave;3. 时序部件我们设置一个时序部件 用于产生读写信号，该部件具有启停功能，可以产生 4 分频的节拍。-timing.vhdlibrary ieee;use ieee.numeric_std.all; use ieee.std_logic_1164.all;entity timing isport (clk:in

11、std_logic; clr:in std_logic; start:in std_logic; stop:in std_logic; t1:out std_logic; t2:out std_logic; t3:out std_logic; t4:out std_logic);end timing;architecture art of timing issignal din:std_logic; signal dout:std_logic; signal r:std_logic; signal s:std_logic:='0' signal tt1:std_logic; s

12、ignal tt2:std_logic; signal tt3:std_logic; signal tt4:std_logic; beginprocess(clr,clk) beginif clr='0' thentt1<='1'tt2<='0'tt3<='0'tt4<='0'elsif(clk'event and clk='1') thentt1<=tt4;tt2<=tt1; tt3<=tt2; tt4<=tt3;end if; end pr

13、ocess;process(tt4,din,clr) beginif clr='0' thendout<='0'elsif tt4'event and tt4='0' then dout<=din;end if; end process;r<=not (clr and stop and s); s<=not (start and r); din<=s;t1<=tt1 and dout; t2<=tt2 and dout; t3<=tt3 and dout; t4<=tt4 and do

14、ut;end art;4. 顶层模块，rw_module这是除等信号模块，将读写信号与时序发生部件产生的时序信号连接起来，并提供启停、清-rw_module.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rw_module isport (clock:in std_logic;clr:in std_logic; start:in std_logic; stop:in std_logic; en_w:in std_logic; en_r:in std_logic;en_addr

15、:buffer std_logic; en_data:buffer std_logic; wr:buffer std_logic; rd:buffer std_logic;raw_in:in std_logic_vector(15 downto 0); data_out:out std_logic_vector(15 downto 0);end rw_module;architecture behave of rw_module issignal addr:std_logic_vector(6 downto 0); signal data:std_logic_vector(15 downto

16、0); component timing isport (clk:in std_logic; clr:in std_logic; start:in std_logic; stop:in std_logic; t1:out std_logic; t2:out std_logic; t3:out std_logic; t4:out std_logic;);end component;component ram isport (address:in std_logic_vector(6 downto 0); data_in:in std_logic_vector(15 downto 0); wr,r

17、d:in std_logic;data_out:out std_logic_vector(15 downto 0);end component;begintimer:timing port map (clk=>clk, clr=>clr, start=>start, stop=>stop, t1=>en_addr, t2=>en_data, t3=>wr, t4=>rd);ramex:ram port map (address=>addr, data_in=>data, wr=>wr and en_w, rd=>rd an

18、d en_r, data_out=>data_out);process(en_addr,raw_in) beginif(en_addr'event and en_addr='1') then addr<=raw_in(6 downto 0);end if;end process;process(en_data,raw_in)beginif(en_data'event and en_data='1') then data<=raw_in;end if; end process;end behave;五、实验步骤在 quartus

19、6.0 下建立工程 sram，添加各模块 vhdl源码。1.2.3.4.编译源码，确认源码编译通过后建立文件，进行，观察波形。led 灯验证。测试后，分配引脚，程序到开发板上观察验证后进行总结。六、实验现象分析验证1. 连续写入内存这里 raw_in 是分时复用的，在第一个节拍的上升沿，通过 raw_in 读入要写入数据的内存地址；在第二个节拍的上升沿，通过 raw_in 读入要写入的数据；在第三个节拍的上升沿写入数据（当 en_w 有效）。时，连续给了四组（地址，数据）：(0x11,0x2121) , (0x12,0xAA45),(0x13,0x8798),(0x14,424F).下面在连续

20、读出的部分进行验证是否正确写入数据。2. 连续读出数据这里我们仍然用 raw_in 给出地址，在第四个节拍的有效期读出数据（当 en_r 有效） 时，我们让 en_r 有效，依次给出四个地址 0x14，0x13, 0x12 ,0x11。可以看到 data_out的值依次为 0x424f,0x8798,0xAA45, 0x2121。这证明了设计的正确性。实机验证分配引脚，编译，计没有问题。到实验板后，可以重复时的操作，根据 led 的显示来看，此设七、实验小结通过实验，学习和掌握了器的工作原理及设计方法；进一步掌握了 VHDL 语言的多层次结构的设计方法和应用；同时感受到了的和重要。可谓是收获良

21、多。实验六数据通路的设计和实现一、实验目的学习和掌握一个基本的数据通路的结构和运行规律进一步掌握 VHDL 语言的层次结构的设计理念进一步掌握 VHDL 的编程技术。二、实验要求1.完成一个数据通路的设计和调试。2.掌握类型的模块的设计和调试。3. 掌握信号发生器的使用及时序的观察。4. 深入掌握 TEC-CA-I 开发板或XJECA 的 I/O 设备的功能的使用。具体实验要求如下：1.画出器的电路图；反映出内部结构与外部端口。2.写出实现模块的VHDL 代码并反映出设计思路（利用流程图、状态图等）3.对数据的传输过程进行，时序波形进行定量的分析；4. 设计和调试过程（配合截图说明）5. 遇到

22、什么问题及如何解决的？6. 数据通路结构模块（见图 1，图 2、图 3）选择或自行设计。三、实验内容1. 利用硬件描述语言 VHDL 实现一个数据通路的连接，包括：RAM、ALU、RF 等模块；2. 观察输入数据后，信号在各部件中的传输情况（状态）；3. 开关量提供输入，通过指示灯观察各模块端口的状态（静态）。4. 由时序发生器模块提供输入信号及时钟 clk，观察和分析各模块端口的状态？（动态）四、设计思路与源代码这里设计一个简单的数据通路，连接 ram，rf，alu。通过这个数据通路可以从外部往指定的内存地址写入数据，将数据写入寄存器组（rf），并且可以从 rf 读出数据到 alu 中参与运

23、算，运算的结果可以写回 rf 或ram。因为只需要突显数据只支持一个加法运算。1.顶层设计的特性，这里的 alu 设计得很简陋，上图顶层设计 datapath 有三个主要的低层设计模块：memory、regfile、alu。-datapath.vhd library ieee;use ieee.std_logic_1164.all;entity datapath isport(clk:in std_logic;en_addr:in std_logic; mem_wr:in std_logic; mem_rd:in std_logic; rf_wr:in std_logic; en_alu:in

24、 std_logic;alu2mem:in std_logic;alu2rf:in std_logic;alu_op:in std_logic_vector(2 downto 0); wr_port:in std_logic_vector(2 downto 0); rd_port1:in std_logic_vector(2 downto 0); rd_port2:in std_logic_vector(2 downto 0); input:instd_logic_vector(15 downto 0); output:out std_logic_vector(15 downto 0);end

25、 datapath;architecture art of datapath issignal alu_srcA:std_logic_vector(15 downto 0); signal alu_srcB:std_logic_vector(15 downto 0); signal address:std_logic_vector(5 downto 0); signal mem_in:std_logic_vector(15 downto 0); signal mem_out:std_logic_vector(15 downto 0); signal rf_in:std_logic_vector

26、(15 downto 0); signal rf_out1:std_logic_vector(15 downto 0); signal rf_out2:std_logic_vector(15 downto 0); signal result:std_logic_vector(15 downto 0);signal alu_out:std_logic_vector(15 downto 0);component memory isPort (clk : inSTD_LOGIC;address : inmem_wr : in mem_rd : in wr_data : inSTD_LOGIC_VEC

27、TOR (5 downto 0);STD_LOGIC; STD_LOGIC;STD_LOGIC_VECTOR (15 downto 0);rd_data : outSTD_LOGIC_VECTOR (15 downto 0);end component;component regfile isport (clk: in std_logic; rf_wr:in std_logic;wr_port:in std_logic_vector(2 downto 0);rd_port1:in std_logic_vector(2 downto 0);rd_port2:in std_logic_vector

28、(2 downto 0);wr_data:in std_logic_vector(15 downto 0); rd_data1:out std_logic_vector(15 downto 0); rd_data2:out std_logic_vector(15 downto 0);end component;component alu isport (en:in std_logic;alu_op:in std_logic_vector(2 downto 0); alu_srcA:in std_logic_vector(15 downto 0); alu_srcB:in std_logic_v

29、ector(15 downto 0); alu_out:out std_logic_vector(15 downto 0); zf:out std_logic;cf:out std_logic);end component;beginmem:memory port map (clk=>clk, address=>address, mem_wr=>mem_wr, mem_rd=>mem_rd, wr_data=>mem_in, rd_data=>mem_out);rf:regfile port map (clk=>clk, rf_wr=>rf_wr

30、, wr_port=>wr_port, rd_port1=>rd_port1, rd_port2=>rd_port2, wr_data=>rf_in, rd_data1=>rf_out1, rd_data2=>rf_out2);alu0:alu port map (en=>en_alu,alu_op=>alu_op,alu_srcA=>alu_srcA, alu_srcB=>alu_srcB, alu_out=>alu_out-ignore zf,cf);process(clk,en_addr)beginif clk'e

31、vent and clk='1' then if en_addr='1' thenaddress<=input(5 downto 0); end if;end if; end process;process(alu2mem,input,alu_out) beginif alu2mem='1' then mem_in<=alu_out;elsemem_in<=input; end if;end process;process(alu2rf,mem_out,alu_out)beginif alu2rf='1' the

32、n rf_in<=result;elserf_in<=mem_out; end if;end process;process(alu_out,clk)beginif clk'event and clk='1' then if en_alu='1' thenresult<=alu_out; end if;end if; end process; output<=result;alu_srcA<=rf_out1;alu_srcB<=rf_out2;end art;3. 低层设计，内存模块这是一个 64x16bit 的 sr

33、am，设计思路与实验五相同-memory.vhdlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity memory isPort (clk : inSTD_LOGIC;address : inmem_wr : in mem_rd : inwr_data : inSTD_LOGIC_VECTOR (5 downto 0);STD_LOGIC; STD_LOGIC;STD_LOGIC_VECTOR (15 downto 0);rd_data

34、: outSTD_LOGIC_VECTOR (15 downto 0);end memory;architecture Behavioral of memory issubtype word is std_logic_vector(15 downto 0);typemem_type is array(0 to 63) of word;signal mem:mem_type;beginprocess(clk,mem_wr,address,mem_rd,wr_data,mem)beginif clk'event and clk='1' then if mem_wr='

35、;1' thenmem(conv_integer(address)<=wr_data; end if;end if;if mem_rd='1' then rd_data<=mem(conv_integer(address);elserd_data<=(others=>'Z'); end if;end process;end Behavioral;4. 低层设计，寄存器组模块这里附上 regfile 和 register_16 的源代码。（为节省篇幅，涉及到的译码器和多路选择器的代码因比较简单且不体现数据通路的逻辑，在此略去。）-r

36、egister_16.vhdlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity register_16 isport (clk:in std_logic;we:in std_logic;- write enabledin:in std_logic_vector(15 downto 0);qout:out std_logic_vector(15 downto 0);end register_16;architecture art of register_16 isbegin process(clk,we,din) beginif clk'eve

37、nt and clk='1' then if we='1' thenqout<=din; end if;end if; end process;end art;-regfile.vhdlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use work.user_type.all;entity regfile isport (clk: in std_logic; rf_wr:in std_logic;wr_port:in std_logic_vector(2 downto 0); rd_port1:in std_logic_v

38、ector(2 downto 0); rd_port2:in std_logic_vector(2 downto 0); wr_data:in std_logic_vector(15 downto 0); rd_data1:out std_logic_vector(15 downto 0); rd_data2:out std_logic_vector(15 downto 0);end regfile;architecture Behavioral of regfile issignal data:word_array;signal dec_out:std_logic_vector(7 down

39、to 0); signal en_wr:std_logic_vector(7 downto 0);component register_16 isport (clk:in std_logic;we:in std_logic;din:in std_logic_vector(15 downto 0);qout:out std_logic_vector(15 downto 0);end component;component mux_8_1 isport (mux_in:in word_array;sel:in std_logic_vector(2 downto 0);mux_out:out std

40、_logic_vector(15 downto 0);end component;component decoder_3_8 isport (sel : instd_logic_vector(2 downto 0); dout: outstd_logic_vector(7 downto 0);end component;beginen_wr(0)<=dec_out(0) and rf_wr; en_wr(1)<=dec_out(1) and rf_wr; en_wr(2)<=dec_out(2) and rf_wr; en_wr(3)<=dec_out(3) and r

41、f_wr; en_wr(4)<=dec_out(4) and rf_wr; en_wr(5)<=dec_out(5) and rf_wr; en_wr(6)<=dec_out(6) and rf_wr; en_wr(7)<=dec_out(7) and rf_wr;dec:decoder_3_8 port map(sel=>wr_port, dout=>dec_out);reg0:register_16 port map (clk=>clk, we=>en_wr(0), din=>wr_data, qout=>data(0);reg1

42、:register_16 port map(clk=>clk, we=>en_wr(1), din=>wr_data, qout=>data(1);reg2:register_16 port map (clk=>clk, we=>en_wr(2), din=>wr_data, qout=>data(2);reg3:register_16 port map (clk=>clk, we=>en_wr(3), din=>wr_data, qout=>data(3);reg4:register_16 port map (clk=&

43、gt;clk, we=>en_wr(4), din=>wr_data, qout=>data(4);reg5:register_16 port map (clk=>clk, we=>en_wr(5), din=>wr_data, qout=>data(5);reg6:register_16 port map (clk=>clk, we=>en_wr(6), din=>wr_data, qout=>data(6);reg7:register_16 port map (clk=>clk,we=>en_wr(7), din

44、=>wr_data, qout=>data(7);mux0:mux_8_1 port map (sel=>rd_port1, mux_in=>data, mux_out=>rd_data1);mux1:mux_8_1 port map (sel=>rd_port2, mux_in=>data, mux_out=>rd_data2);end Behavioral;5. 低层设计，alu此处的 alu 为了简便只涉及加法运算-alu.vhdlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LO

45、GIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL;entity alu is port(en:in std_logic;alu_op:in std_logic_vector(2 downto 0);alu_srcA:in std_logic_vector(15 downto 0);alu_srcB:in std_logic_vector(15 downto 0); alu_out:out std_logic_vector(15 downto 0); zf:out std_logic;cf:out std_logic);end alu;architecture

46、 Behavioral of alu issignal a: std_logic_vector(15 downto 0):=(others=>'0'); signal b: std_logic_vector(15 downto 0):=(others=>'0'); signal cin: std_logic:='0'signal carry: std_logic:='0'signal result: std_logic_vector(15 downto 0):=(others=>'0'); sig

47、nal sel: std_logic_vector(7 downto 0):=(others=>'0');component alu_add isPort (en:in std_logic;a : instd_logic_vector (15 downto 0); b : instd_logic_vector (15 downto 0); cin : instd_logic;sum : outstd_logic_vector (15 downto 0); ov : outstd_logic);end component;beginprocess(alu_op,en,alu

48、_srcA,alu_srcB) begincase alu_op iswhen "000"=>-decide sub or adda<=alu_srcA;b<=alu_srcB; cin<='0'-addsel(0)<='1' and en;when others=> null;end case; end process;adder:alu_add port map (en=>sel(0),a=>a,b=>b,cin=>cin, sum=>result, ov=>carr

49、y);process(result) beginif result=0 then zf<='1'elsezf<='0'end if; end process;cf<=carry;alu_out<=result; end Behavioral;-adder_4bit(4 位并行加法器，用于构建 16 位加法器) library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity adder_4bit is Port(en:in std_logic;a : instd_logic_vector (3 downto

50、0); b : instd_logic_vector (3 downto 0); cin : instd_logic;sum : outstd_logic_vector (3 downto 0); cout : outstd_logic);end adder_4bit;architecture Behavioral of adder_4bit is beginprocess(en,a,b,cin)variable c:std_logic_vector(4 downto 0); variable p:std_logic_vector(3 downto 0); variable g:std_log

51、ic_vector(3 downto 0); beginif(en='1') thenc(0):=cin; p:=a xor b; g:=a and b;c(1):= g(0) or (p(0) and c(0);c(2):= g(1) or (p(1) and g(0) or (p(1) and p(0)and c(0);c(3):= g(2) or (p(2) and g(1) or (p(2) and p(1) and g(0) or (p(2) and p(1) and p(0)and c(0);c(4):= g(3) or (p(3) and g(2) or (p(3

52、) and p(2) and g(1)or (p(3) and p(2) and p(1)and g(0) or (p(3) and p(2) and p(1)and p(0)and c(0);sum<=p xor c(3 downto 0);cout<=c(4);elsesum<=(others=>'Z');cout<='0' end if;end process; end Behavioral;-alu_add.vhd，十六位加法器 采用分组级联library IEEE;use IEEE.STD_LOGIC_1164.ALL;e

53、ntity alu_add is Port(en:in std_logic;a : instd_logic_vector (15 downto 0); b : instd_logic_vector (15 downto 0); cin : instd_logic;sum : outstd_logic_vector (15 downto 0); ov : outstd_logic);end alu_add;architecture Behavioral of alu_add is signal c4:std_logic;signal c8:std_logic; signal c12:std_logic;component adder_4bit is Port(en