基于FPGA的日历时间闹铃系统

1、基于FPGA的日历、时间、闹铃系统前言：由于本人刚刚入门，只用了最基本的设计思维，所以可能浪费了许多芯片资源，要是哪位高手能帮忙把系统优化一下，本人定然感激不尽。系统功能：显示当前日期，时间，到点报时。可通过按键来调整日期时间，并且设置闹铃时间，闹铃响后，必须手动关闭。模块说明：系统的顶层模块如下图所示，该系统由六个模块组成，分别为分频模块，按键模块，计数模块，LCD液晶显示模块，除法器模块，以及铃声模块。皆为可综合模块，可综合为门级网表，并在FPGA芯片上验证了其正确性。由于涉及版权问题，严禁用于商业目的，违者必究！按键示意图： 各模块的verilog代码如下：1,、分频器：mod

2、ule div_1hz(clk,clock);output reg clock;input clk;/外部50MHZ时钟输入reg24:0 i;always(posedge clk) begin  i=i+1;  if(i=25'h17d7840)   begin     i=0;     clock=clock; /产生1HZ频率信号。   end endendmodule2、

3、按键模块：module key(num,keyout,targe,keyout_en,keyin,rst,clk);output reg 3:0 keyout;output 3:0 num;output targe;output reg keyout_en;input rst,clk;input 3:0keyin;reg 7:0 i;reg 3:0 num;reg 23:0 count;reg 5:0 state,next_state;reg 3:0 keyout_reg,keyin_reg;parameter   s0=6'b000001,  

4、 s1=6'b000010,   s2=6'b000100,    s3=6'b001000,   s4=6'b010000,   s5=6'b100000;wire clock;always(posedge clk or negedge rst) begin  if(!rst)   i<=0;  else  i

5、<=i+1;  endassign clock=i7;always(posedge clock or negedge rst) begin  if(!rst)   begin    count<=0;    keyout_en<=0;   end  else begin   if(keyin!=4'hf)  &#

6、160; begin     if(count<'h4bb3)/去抖动     count<=count+1;     else     keyout_en<=1;    end   else if(state5|state0)    begin

7、0;    count<=0;     keyout_en<=0;    end   end endassign targe=(!(state=s0|state=s5)&&(keyin!=4'hf);always(posedge clock) begin  if(targe)   begin   key

8、out_reg<=keyout;   keyin_reg<=keyin;   end  else   begin   keyout_reg<=keyout_reg;   keyin_reg<=keyin_reg;   end end always(keyout_reg or keyin_reg or clock) begin 

9、0;case(keyin_reg,keyout_reg)   8'b1110_1110: num <= 1 ;   8'b1110_1101: num <= 2 ;   8'b1110_1011: num <= 3 ;   8'b1110_0111: num <= 10 ;      8'b1101_1110: num <= 4 ; &#

10、160; 8'b1101_1101: num <= 5 ;   8'b1101_1011: num <= 6 ;   8'b1101_0111: num <= 11 ;      8'b1011_1110: num <= 7 ;   8'b1011_1101: num <= 8 ;   8'b1011_1011: num <

11、= 9;   8'b1011_0111: num <= 12;      8'b0111_1110: num <= 0;   8'b0111_1101: num <= 15;   8'b0111_1011: num <= 14;   8'b0111_0111: num <= 13;     

12、0;          endcase  end always(posedge clock or negedge rst) begin  if(!rst)   state<=s0;  else   state<=next_state; end always(keyin or state or keyout_en) begin  

13、; keyout=4'b0000;  case(state)   s0:  begin     keyout=4'b0000;     if(keyout_en)      next_state=s1;     else      next_s

14、tate=s0;    end   s1: begin     keyout=4'b1110;     if(keyin!=4'hf)      next_state=s5;     else      next_state=s2;&

15、#160;   end   s2: begin     keyout=4'b1101;     if(keyin!=4'hf)      next_state=s5;     else      next_state=s3; 

16、0;  end   s3: begin     keyout=4'b1011;     if(keyin!=4'hf)      next_state=s5;     else      next_state=s4;    

17、end   s4: begin     keyout=4'b0111;     if(keyin!=4'hf)      next_state=s5;     else      next_state=s0;    end 

18、  s5: begin     keyout=4'b0000;     if(keyin=4'hf)      next_state=s0;     else      next_state=s5;    end  

19、0;default next_state=s0;  endcase endendmodule计数器模块：module jishuqi(out_4,out_400,nian,yue,ri,  shi,fen,miao,n,speaker,ns,nf,clk_1hz,yushu1,yushu2,num,keyout_en);/shuzimiaobiaooutput reg15:0nian; output reg7:0yue,ri,shi,fen,miao,ns,nf;output 11:0 out_4,out_400;output reg

20、 1:0n;output reg speaker;input clk_1hz;input 15:0yushu1,yushu2;input 3:0 num;input  keyout_en;reg 3:0cunt;reg2:0 cnt;reg 15:0 ni;reg 7:0 y,r,s,f,m;assign out_4='d4;assign out_400='d400;wire 15:0yushu;assign yushu=!(yushu1=0)|(yushu2=0)?0:1;initial begin ns<=8;speaker<=1;endalways(

21、posedge clk_1hz)begin if(n=3)  begin speaker<=1;end else if(shi=ns)&&(fen=nf)  begin speaker<=0;end else  speaker<=speaker;endalways(negedge keyout_en)begin if(num='ha)  begin n<=1;cunt<=0;end else if(num=

22、9;hd)  begin   n<=0;  cunt<=0;  cnt<=0;  end else if(num='hb)  n<=2; else if(num='hc)  n<=3; else  n<=n; if(n=2)  begin   if(num=1)|(num=2)|(num=3)|(

23、num=4)|(num=5)|(num=6)   |(num=7)|(num=8)|(num=9|num=0)        begin cnt<=cnt+1;end   else    cnt<=cnt;  end   if(n=1)  begin   if(num=1)|(num=2)|(num=3)|

24、(num=4)|(num=5)|(num=6)   |(num=7)|(num=8)|(num=9|num=0)        begin cunt<=cunt+1;end   else    cunt<=cunt;  end case(cnt)  0:ns7:4<=num;  1:ns3:0<=num; 

25、0;2:nf7:4<=num;  3:nf3:0<=num;  4:cnt<=0; endcase   case(cunt)  0:begin ni15:12<=num;end  1:begin ni11:8<=num;end  2:begin ni7:4<=num;end  3:begin ni3:0<=num;end  4:begin y7:4<=num;end&#

26、160; 5:begin y3:0<=num;end  6:begin r7:4<=num;end  7:begin r3:0<=num;end  8:begin s7:4<=num;end  9:begin s3:0<=num;end  10:begin f7:4<=num;end  11:begin f3:0<=num;end  12:begin m7:4<=num;end  

27、;13:begin m3:0<=num;end  14:cunt<=0; endcaseend  always(posedge clk_1hz)/suan fa shi xianbeginif(n!=1)beginmiao<=miao+1;      if(yue='h13)       begin        

28、;      yue<=0;              nian3:0<=nian3:0+1;       if(nian3:0='d9)        begin     

29、60;  nian3:0<=0;        nian7:4<=nian7:4+1;        if(nian7:4='d9)         begin         nian7:4<=0; &

30、#160;       nian11:8<=nian11:8+1;         if(nian11:8='d9)          begin          nian11:8<=0;  

31、60;       nian15:12<=nian15:12+1;          if(nian15:12='d9)           nian15:12<=0;          end

32、60;        end        end       endif(miao3:0=4'd9) begin miao3:0<=0; miao7:4<=miao7:4+1; if(miao7:4=4'd5)  begin  miao7:4<=0;&#

33、160; fen3:0<=fen3:0+1;   if(fen3:0=9)   begin   fen3:0<=0;   fen7:4<=fen7:4+1;   if(fen7:4=4'd5)    begin    fen7:4<=0;    shi3:0<=shi3:0+1;&

34、#160;   if(shi3:0='d9)     begin     shi3:0<=0;     shi7:4<=shi7:4+1;     end    if(shi7:4=2)&&(shi3:0=3)     begin &

35、#160;   shi7:4<=0;     shi3:0<=0;     ri3:0<=ri3:0+1;     if(ri3:0='d9)      begin      ri3:0<=0;      r

36、i7:4<=ri7:4+1;      end     if(yue3:0=1)&&(yue7:4=0)|(yue3:0=3)&&(yue7:4=0)|(yue3:0=5)|(yue3:0=7)|(yue3:0=8)|       (yue3:0=0)&&(yue7:4=1)|(yue3:0=2)&&(yue7:4=1)|(yue3:0=3)&am

37、p;&(yue7:4=1)      begin      if(!(yue3:0=3)&&(yue7:4=1)       begin       if(ri7:4=3)&&(ri3:0=1)        begin

38、        ri7:4<=0;        ri3:0<=1;        yue3:0<=yue3:0+1;        end       end  

39、0;        if(yue3:0=4)|(yue3:0=6)|(yue3:0=9)|(yue3:0=1)&&(yue7:4=1)      begin      if(ri7:4=3)&&(ri3:0=0)       begin     &

40、#160; ri7:4<=0;       ri3:0<=1;       yue3:0<=yue3:0+1;       end      end     if(yue3:0=2)&&(yue7:4=0)  

41、60;   begin      if(yushu=0)       begin       if(ri7:4=2)&&(ri3:0=9)        begin        ri7:4&l

42、t;=0;        ri3:0<=1;        yue3:0<=yue3:0+1;        end       end      else     &

43、#160; begin       if(ri7:4=2&&ri3:0=9)        begin        ri7:4<=0;        ri3:0<=1;       

44、; yue3:0<=yue3:0+1;        end       end      end     if(yue3:0='d10)      begin      yue3:0<=0

45、;      yue7:4<=yue7:4+1;      end     end    end   end  end endendend if(n=1) begin nian<=ni; yue<=y; ri<=r; shi<=s;

46、0;fen<=f; miao<=m; endendendmodule4、LCD液晶显示模块：module lcd1602(nian,yue,ri,shi,fen,miao,clk,n,ns,nf,rs,rw,en,dat);function 7:0data;input 3:0 num;begin case(num)  0:begin data=8'h30;end  1:data=8'h31;  2:data=8'h32;  3:data=8'

47、h33;  4:data=8'h34;  5:data=8'h35;  6:data="6"  7:data=8'h37;  8:data=8'h38;  9:data=8'h39; endcaseendendfunctioninput 15:0 nian;input 7:0 yue,ri,shi,fen,miao;input 7:0ns,nf;input clk;input 1:0 n;output rs

48、,rw,en;output7:0 dat;reg rs,rw;wire en;reg7:0 dat;reg5:0 counter;reg1:0 state;reg 15:0 count; reg clkr; parameter init=0,write_data=1;assign en=clkr;always (posedge clk)      begin count=count+1; if(count=16'h000f) clkr=clkr; end always(posedge clkr)begin  

49、0; case(state)  init:   begin    rs=0;rw=0;    counter=counter+1;    case(counter)      1:dat='h38;      2:dat='h08;      3:dat='h01; 

50、0;    4:dat='h06;      5:dat='h0c;      6:       begin        dat='h80;        state=write_data;    

51、60;   counter=0;        end       default: counter=0;      endcase   end                   

52、0;  write_data:                begin     if(n!=2)      begin         case(counter)       &

53、#160;  0:begin rs<=0;dat=0+8'h80;end          1:begin rs<=1;dat=data(nian15:12);end          2:begin rs<=0;dat=1+8'h80;end          3:begin rs&

54、lt;=1;dat=data(nian11:8);end          4:begin rs<=0;dat=2+8'h80;end          5:begin rs<=1;dat=data(nian7:4);end          6:begin rs<=0;dat=3+8'h80;

55、end          7:begin rs<=1;dat=data(nian3:0);end          8:begin rs<=0;dat=4+8'h80;end          9:begin rs<=1;dat="-"end   

56、60;      10:begin rs<=0;dat=5+8'h80;end          11:begin rs<=1;dat=data(yue7:4);end          12:begin rs<=0;dat=6+8'h80;end       &#

57、160;  13:begin rs<=1;dat=data(yue3:0);end          14:begin rs<=0;dat=7+8'h80;end          15:begin rs<=1;dat="-"end          16:begin rs

58、<=0;dat=8+8'h80;end          17:begin rs<=1;dat=data(ri7:4);end          18:begin rs<=0;dat=9+8'h80;end          19:begin rs<=1;dat=data(ri3:0);e

59、nd        20:begin rs<=0;dat=0+8'hc0;end          21:begin rs<=1;dat=data(shi7:4);end          22:begin rs<=0;dat=1+8'hc0;end    

60、0;     23:begin rs<=1;dat=data(shi3:0);end          24:begin rs<=0;dat=2+8'hc0;end          25:begin rs<=1;dat=":"end        &#

61、160; 26:begin rs<=0;dat=3+8'hc0;end          27:begin rs<=1;dat=data(fen7:4);end          28:begin rs<=0;dat=4+8'hc0;end          29:begin rs<=1;

62、dat=data(fen3:0);end          30:begin rs<=0;dat=5+8'hc0;end          31:begin rs<=1;dat=":"end          32:begin rs<=0;dat=6+8'hc0;end

63、60;         33:begin rs<=1;dat=data(miao7:4);end          34:begin rs<=0;dat=7+8'hc0;end          35:begin rs<=1;dat=data(miao3:0);end    

64、;      36:          begin            rs=0; dat='h80;          end       

65、0;  default: counter=0;       endcase       if(counter=37) counter=0;       else counter=counter+1;      end        

66、0; else      begin       case(counter)          0:begin rs<=0;dat=0+8'h80;end          1:begin rs<=1;dat=data(ns7:4);end 

67、0;        2:begin rs<=0;dat=1+8'h80;end          3:begin rs<=1;dat=data(ns3:0);end          4:begin rs<=0;dat=2+8'h80;end      &

68、#160;  5:begin rs<=1;dat=":"end          6:begin rs<=0;dat=3+8'h80;end          7:begin rs<=1;dat=data(nf7:4);end        8:begin rs<=0;dat=

69、4+8'h80;end        9:begin rs<=1;dat=data(nf3:0);end        10:begin rs<=0;dat=5+8'h80;end          11:begin rs<=1;dat=" "end    

70、;      12:begin rs<=0;dat=6+8'h80;end          13:begin rs<=1;dat=" "end          14:begin rs<=0;dat=7+8'h80;end       

71、0;  15:begin rs<=1;dat=" "end          16:begin rs<=0;dat=8+8'h80;end          17:begin rs<=1;dat=" "end          18:begin rs&l

72、t;=0;dat=9+8'h80;end          19:begin rs<=1;dat=" "end        20:begin rs<=0;dat=0+8'hc0;end          21:begin rs<=1;dat=" "end 

73、;         22:begin rs<=0;dat=1+8'hc0;end          23:begin rs<=1;dat=" "end          24:begin rs<=0;dat=2+8'hc0;end    

74、0;     25:begin rs<=1;dat=" "end          26:begin rs<=0;dat=3+8'hc0;end          27:begin rs<=1;dat=" "end        &#

75、160; 28:begin rs<=0;dat=4+8'hc0;end          29:begin rs<=1;dat=" "end          30:begin rs<=0;dat=5+8'hc0;end          31:begin rs<=1;

76、dat=" "end          32:begin rs<=0;dat=6+8'hc0;end          33:begin rs<=1;dat=" "end          34:begin rs<=0;dat=7+8'hc0;end

77、60;         35:begin rs<=1;dat=" "end        36: begin            rs=0; dat='h80;         

78、60;end          default:counter<=0;       endcase       if(counter=37) counter<=0;       else counter<=counter+1;    

79、;  end                end                 default: state=init;        endcaseendendmodule5、除法器模块， &#

80、160;  module divider(quotient,remainder,ready,error,word1,word2,start,clock,reset);parameter   L_divn=16,            L_divr=12,            S_idle=0,S_adivr=1,S_adivn=2,S_

81、div=3,S_err=4,            L_state=3,L_cnt=4,Max_cnt=L_divn-L_divr;output  L_divn-1:0   quotient,remainder;output                 ready,error;input

82、0;  L_divn-1:0   word1;/dividendinput   L_divr-1:0   word2;/divisorinput                  start,clock,reset;/0,start,1,resetreg     L_state-1:0  state,next

83、_state;reg                    Load_words,Subtract,Shift_dividend,Shift_divisor;reg     L_divn-1:0   quotient;reg     L_divn:0     divid

84、end;reg     L_divr-1:0   divisor; reg     L_cnt-1:0    num_Shift_dividend,num_Shift_divisor;reg     L_divr:0     comparison;wire    MSB_divr=divisorL_divr-1;wire   

85、ready=(state=S_idle)&&reset);wire    error=(state=S_err);wire    Max=(num_Shift_dividend=Max_cnt+num_Shift_divisor);wire    sign_bit=comparisonL_divr;assign  remainder=(dividendL_divn-1:L_divn-L_divr)>num_Shift_divisor;/always (state or di

86、vidend or divisor or MSB_divr)   case(state)      S_adivr:   if(MSB_divr=0)                    comparison=dividendL_divn:L_divn-L_divr+1'b1,(divisor<<

87、1)+1'b1;                 else                    comparison=dividendL_divn:L_divn-L_divr+1'b1,divisorL_divr-1:0+1'

88、;b1;      default:   comparison=dividendL_divn:L_divn-L_divr+1'b1,divisorL_divr-1:0+1'b1;   endcase always (posedge clock or negedge reset)  if(!reset) state<=S_idle; else state<=next_state;always (state or word1 or word2 or start

89、or comparison or sign_bit or Max)  begin    Load_words=0;Subtract=0;Shift_dividend=0;Shift_divisor=0;      case(state)           S_idle:    case(!start)      &#

90、160;                 0:  next_state=S_idle;                        1:  if(word2=0) next_state=S

91、_err;                            else if(word1) begin next_state=S_adivr;Load_words=1; end            

92、60;               else next_state=S_idle;                      endcase         &

93、#160; S_adivr:   case(MSB_divr)                        0:  if(sign_bit=0) begin next_state=S_adivr;Shift_divisor=1; end        

94、60;                   else if(sign_bit=1) next_state=S_adivn;                        1:  n

95、ext_state=S_div;                      endcase           S_adivn:   case(Max,sign_bit)        &#

96、160;               2'b00:  next_state=S_div;                        2'b01:  begin next_state=S_ad

97、ivn;Shift_dividend=1; end                        2'b10:  begin next_state=S_idle;Subtract=1; end             &#

98、160;          2'b11:  next_state=S_idle;                      endcase           S_div: 

99、;    case(Max,sign_bit)                        2'b00:  begin next_state=S_div;Subtract=1; end           &#

100、160;            2'b01:  next_state=S_adivn;                        2'b10:  begin next_state=S_div;Subtract=1; en

101、d                        2'b11:  begin next_state=S_div;Shift_dividend=1; end                

102、60;     endcase           default:   next_state=S_err;       endcase   endalways (posedge clock or negedge reset)begin  if(!reset)     begin   &#

103、160;    divisor<=0;       dividend<=0;       quotient<=0;       num_Shift_dividend<=0;       num_Shift_divisor<=0;     end  e

104、lse if(Load_words=1)     begin       dividend<=word1;       divisor<=word2;       quotient<=0;       num_Shift_dividend<=0;    &

105、#160;  num_Shift_divisor<=0;     end  else if(Shift_divisor)     begin       divisor<=divisor<<1;       num_Shift_divisor<=num_Shift_divisor+1;     end

106、0; else if(Shift_dividend)     begin       dividend<=dividend<<1;       quotient<=quotient<<1;       num_Shift_dividend<=num_Shift_dividend+1;     en

107、d  else if(Subtract)     begin       dividendL_divn:L_divn-L_divr<=comparison;       quotient0<=1;     endendendmodule6、铃声模块：module liangzhu(sys_clk,rst_n,sp); input   s

108、ys_clk,rst_n; output  sp;  reg    sp; reg3 :0 high,med,low; reg13:0 divider,origin; reg7 :0 counter; reg23:0 clk_cnt;   always (posedge sys_clk or posedge rst_n)    if (rst_n)  

109、60;     clk_cnt <= 24'd0;    else        clk_cnt <= clk_cnt + 1'b1; wire  clk_6mhz = clk_cnt2; wire  clk_4hz  = clk_cnt23; wire carry=(divider=16383); always (posedge clk_6mhz) 

110、; begin     if(carry)    divider=origin;      else            divider=divider+1'b1;  end always(posedge carry)   begin      sp

111、 =sp;   end      always(posedge clk_4hz)   begin     case(high ,med ,low)      12'b000000000011: origin=14'd7281;      12'b000000000101: origin=14'd8730;  

112、0;   12'b000000000110: origin=14'd9565;      12'b000000000111: origin=14'd10310;      12'b000000010000: origin=14'd10647;      12'b000000100000: origin=14'd11272;&

113、#160;     12'b000000110000: origin=14'd11831;      12'b000001010000: origin=14'd12556;      12'b000001100000: origin=14'd12974;      12'b000100000000: origin=14'd13516;      12'b000000000000: origin=14'd16383;  default: