VHDL语法格式

1、VHDL语法格式上篇 基础元素目录： 数据类型 数据对象 运算符 语句 基本程序结构 电路描述方式数据类型 预定义类型 bit bit_victor integer std_logic std_logic_victor 自定义类型 枚举类型 type 新数据类型 is (元素1, 元素2, .) 例 定义 type state_type is (s1, s2, s3. s4);- 定义一个新类型state_type 引用 signal state : state_type;- 定义一个信号state，类型为state_type 数组类型 type 数组 is array (范围) of 数据类

2、型; 例 定义 type byte is array (7 downto 0) of bit;- 定义一个8bit的数组 type word is array (31 downto 0) of bit;- 定义一个32bit的数组数据对象 端口 声明端口 : in | out 数据类型; - 端口在特性上等同于信号，但赋值在entity的port中赋值端口 <= 表达式; 信号 声明signal 信号 : 数据类型;赋值信号 <= 表达式; 变量 声明varable 变量 : 数据类型;赋值变量 := 表达式; 常数 声明常数 : 数据类型 := 数值;运算符 算术运算 +, -,

3、 * 并置运算 & 关系运算 =, /=, <, <=, >, >= 逻辑运算 and, or, not, nand, nor, xor, xnor语句 并行语句 信号赋值语句 简单信号赋值语句 信号 <= 表达式; 选择信号赋值语句 with 选择表达式 select 信号 <= 表达式1 when 选择值1, 表达式2 when 选择值2, . 表达式n when others; 条件信号赋值语句 信号 <= 表达式1 when 条件关系式1 else 表达式2 when 条件关系式2 else . 表达式n when 条件n else 表

4、达式; 过程调用语句 过程 (实参); 函数调用语句 信号 <= 函数 (实参); 元件例化语句 元件声明 component 元件实体 - 将一个实体声明为元件 port (端口声明); end component; 元件引用 按位置引用 标号 : 元件实体 port map (连接端口1, 连接端口2, .); 按名称引用 标号 : 元件实体 port map (元件端口1 >= 连接端口1, 元件端口2 >= 连接端口2, .); 生成语句 格式 1 标号: for 循环变量 in 取值范围 generate 声明语句, begin 并行语句, end generate

5、 标号; 取值范围: 表达式 to 表达式; - 递增方式，如1 to 5 表达式 downto 表达式 ; - 递减方式，如5 downto 1 格式 2 标号: if 条件关系式 generate 声明语句; begin 并行语句, end generate 标号 , 块语句 块标号: block (保护条件) 接口声明; 类属声明; begin 并行语句; - 被保护的变量前需加上保留字guarded end block 块标号; 带保护的块语句举例: entity latch is port( d, clk : in bit; q, qb : out bit ); end latch;

6、 achetectire latch_guard of latch is begin b1 : block(clk = ¢1¢) begin q <= guarded d after 5 ns; qb <= guarded not(d) after 7 ns; end block b1; end latch_guard 进程语句 标号: process (敏感信号) 声明语句; -常量，变量，信号 begin 顺序语句; end process 标号:;顺序语句 赋值语句 - 在进程中 信号 <= 表达式; 变量 := 表达式; 流程控制语句 if语句 格

7、式 1: if 条件关系式 then 顺序语句; end if; 格式 2: if 条件关系式 then 顺序语句; else 顺序语句; end if; 格式 3: if 条件关系式1 then 顺序语句; elsif 条件关系式2 then 顺序语句; . else 顺序语句; end if; case 语句 - case 语句中，条件值有3种形式：值，值1 | 值2 |.| 值n，值 TO 值 - 最后一行的顺序语句若为null,则有意引入锁存器 case 条件表达式 is when 条件值 => 顺序语句; . when others => 顺序语句; end case;

8、for_loop 语句 标号: for 循环变量 in 值 to 值 loop; 顺序语句; end loop 标号;时钟边沿描述 上升沿 时钟¢event and时钟 = ¢1¢ | rising_edge (时钟) 下降沿 时钟¢event and时钟 =¢0¢ | falling_edge (时钟)程序基本结构- 主程序与元件程序在同一文件work1.vhd中，library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std

9、_logic_arith.all;- 主程序entity 实体名 is -实体名必须与文件名相同 port (端口声明; );end entity work1;architecture struc of work1 is 声明语句; -常量，变量，信号，元件，函数等begin 并行语句;end architecture struc;电路描述方式 行为描述方式 以用状态机描述电路为典型 数据流 ( 寄存器 ) 描述方式 即用逻辑表达式描述电路 结构描述方式 以用元件复用的方式描述电路为典型VHDL语法格式下篇 复合元素和状态机目录元件 - 1 单文件元件 2 多文件元件函数 - 3 单文件函数

10、4 多文件函数过程 - 5 单文件过程 6 多文件过程moorl 状态机 - 7 二进程moorl状态机 8 三进程moorl状态机meaky 状态机 - 9 二进程mealy状态机 10 三进程mealy状态机状态机实例 - 11 交通灯之一 12 交通灯之二附录 - 13 状态转移图 14 用户库的格式和用法单文件元件- 主程序与元件程序在同一文件work1.vhd中，library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;- 主程序entity work1 is port ( r,s,t,u : i

11、n std_logic; v : out std_logic );end entity work1;architecture struc of work1 is component ym - 将实体ym声明为元件 port ( a,b : in std_logic; c : out std_logic ); end component ym; component hm - 将实体hm声明为元件 port ( a,b : in std_logic; c : out std_logic ); end component hm; signal temp1,temp2 : std_logic;begi

12、n u1 : ym port map ( r, s, temp1 ); - 元件例化 u2 : ym port map ( t, u, temp2 ); u3 : hm port map ( temp1, temp2, v );end architecture struc;- ym元件实体定义程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ym is port ( a,b : in std_logic; c : out std_logic );end entity ym;arch

13、itecture ym1 of ym isbegin c <= a and b;end architecture ym1;- hm元件实体定义程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hm is port ( a,b : in std_logic; c : out std_logic );end entity hm;architecture hm1 of hm isbegin c <= a or b;end architecture hm1;多文件元件- 主程序

14、文件和定义元件的程序文件都要添加到工程中- 主程序文件zhu_map.vhd，不需要声明用户库文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zhu_map is port ( r,s,t,u : in std_logic; v : out std_logic );end entity zhu_map;architecture niu of zhu_map is component ym port ( a,b : in std_logic; c : out std_logic )

15、; end component ym; component hm port ( a,b : in std_logic; c : out std_logic ); end component hm; signal temp1,temp2 : std_logic;begin u1 : ym port map ( r, s, temp1 ); - 元件例化 u2 : ym port map ( t, u, temp2 ); u3 : hm port map ( temp1, temp2, v );end architecture niu;- 定义元件实体的程序文件- ym元件实体定义程序librar

16、y ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ym is port ( a,b : in std_logic; c : out std_logic );end entity ym;architecture ym1 of ym isbegin c <= a and b;end architecture ym1;- hm元件实体定义程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

17、 hm is port ( a,b : in std_logic; c : out std_logic );end entity hm;architecture hm1 of hm isbegin c <= a or b;end architecture hm1;单文件函数library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity func is port ( din1,din2 : in std_logic_vector( 0 to 3 ); dout : out std_logic_vec

18、tor( 0 to 3 ) );end entity;architecture a of func is- 定义函数 function ls_xj ( d1, d2 : in std_logic_vector( 0 to 3 ) ) return std_logic_vector is variable temp : std_logic_vector( 0 to 3 ); begin temp := d1 + d2; return temp; end function;- 定义函数结束begin dout <= ls_xj ( din1, din2 ); -调用函数end archite

19、cture;多文件函数- 主程序文件和定义函数的程序文件都要添加到工程中- 主程序文件zhu_func.vhd，必须声明用户库文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;use work.use_func.all; - use_func.vhd作为用户库entity zhu_func is port ( din1,din2 : in std_logic_vector( 0 to 3 ); dout : out std_logic_vector( 0 to 3 ) );end;architect

20、ure niu of zhu_func isbegin dout <= ls_xj ( din1, din2 ); - 调用函数end;- 定义函数的文件fu_func.vhdlibrary ieee;use ieee.std_logic_1164.all;package use_func is - 声明 function ls_xj ( d1, d2: in std_logic_vector( 0 to 3 ) ) return std_logic_vector;end use_func;package body use_func is - 程序体 function ls_xj ( d

21、1, d2 : in std_logic_vector( 0 to 3 ) ) return std_logic_vector is variable temp : std_logic_vector( 0 to 3 ); begin temp := d1 and d2; return temp; end function;end use_func;单文件过程library ieee;use ieee.std_logic_1164.all;entity call_proce is port ( d1 : in integer range 0 to 31; d2 : in integer rang

22、e 0 to 31; fout : out integer range 0 to 31 ); end;architecture a of call_proce is- 过程定义 procedure jfq ( din1, din2 : in integer range 0 to 31;dout : out integer range 0 to 31 ) is begin dout := din1 + din2; end;- 过程定义结束begin process ( d1, d2 ) variable fo : integer range 0 to 31; begin jfq ( d1, d2

23、, fo ); - 调用过程 fout <= fo; end process;end;多文件过程- 主程序文件和定义过程的程序文件都要添加到工程中- 主程序文件zhu_proc.vhd，必须声明用户库文件library ieee;use ieee.std_logic_1164.all;use work.use_proc.all; - use_proc.vhd作为用户库entity zhu_proc is port ( d1, d2 : in integer range 0 to 31; fout : out integer range 0 to 31 ); end;architectur

24、e niu of zhu_proc isbegin process ( d1, d2 ) variable fo : integer range 0 to 31; begin jfq ( d1, d2, fo ); - 调用过程 fout <= fo; end process;end;- 定义过程的文件fu_proc.vhdlibrary ieee;use ieee.std_logic_1164.all;package use_proc is - 声明 procedure jfq ( din1 : in integer range 0 to 31;din2 : in integer ra

25、nge 0 to 31;dout : out integer range 0 to 31 );end use_proc;package body use_proc is - 程序体 procedure jfq ( din1, din2 : in integer range 0 to 31;dout : out integer range 0 to 31 ) is begin dout := din1 + din2; end jfq;end use_proc;二进程moorl状态机library ieee;use ieee.std_logic_1164.all;entity moorl_1 is

26、port ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_logic_vector ( 2 downto 0 ) );end entity;architecture statemachine of moorl_1 is type state_type is ( s0, s1, s2, s3 ); signal state : state_type;begin process( reset, clock ) - 变换状态 begin if reset = '1' th

27、en state <= s0; elsif rising_edge( clock ) then case state is when s0 => if din = '1' then state <= s1; end if; when s1 => if din = '1' then state <= s2; end if; when s2 => if din = '1' then state <= s3; end if; when s3 => if din = '1' then sta

28、te <= s0; else state <= s1; end if; end case; end if; end process; process( state ) - 输出 begin case state is when s0 => dout <= "001" when s1 => dout <= "011" when s2 => dout <= "101" when s3 => dout <= "111" end case; end process

29、;end;三进程moorl状态机library ieee;use ieee.std_logic_1164.all;entity moorl_2 isport ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_logic_vector( 2 downto 0 ) );end entity;architecture statemachine of moorl_2 is type state_type is ( s0, s1, s2, s3 ); signal presentstate :

30、 state_type; signal nextstate : state_type;begin process ( reset, clock ) - 更新当前状态 begin if reset = '1' then presentstate <= s0; elsif rising_edge ( clock ) then presentstate <= nextstate; end if; end process; process ( presentstate, din ) - 生成下一个状态 begin case presentstate is when s0 =

31、> if din = '1' then nextstate <= s1; else nextstate <= s0; end if; -dout <= "001" when s1 => if din = '1' then nextstate <= s2; else nextstate <= s1; end if; -dout <= "011" when s2 => if din = '1' then nextstate <= s3; else ne

32、xtstate <= s2; end if; -dout <= "101" when s3 => if din = '1' then nextstate <= s0; else nextstate <= s1; -dout <= "111" end if; end case; end process; process ( presentstate ) - 输出 begin case presentstate is when s0 => dout <= "001" when

33、 s1 => dout <= "011" when s2 => dout <= "101" when s3 => dout <= "111" end case; end process;end;二进程mealy状态机library ieee;use ieee.std_logic_1164.all;entity mealy_1 isport ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_

34、logic_vector ( 2 downto 0 ) );end entity;architecture statemachine of mealy_1 is type state_type is ( s0, s1, s2, s3 ); signal state : state_type;begin process ( reset, clock ) - 变换状态 begin if reset = '1' then state <= s0; elsif rising_edge ( clock ) then case state is when s0 => if di

35、n = '1' then state <= s1; end if; when s1 => if din = '1' then state <= s2; end if; when s2 => if din = '1' then state <= s3; end if; when s3 => if din = '1' then state <= s0; else state <= s1; end if; end case; end if; end process; process ( s

36、tate, din ) - 输出 begin case state is when s0 => if din='0' then dout <="000" else dout <="001" end if; when s1 => if din='0' then dout <="010" else dout <="011" end if; when s2 => if din='0' then dout <="100

37、" else dout <="101" end if; when s3 => if din='0' then dout <="110" else dout <="111" end if; end case; end process;end architecture;三进程mealy状态机library ieee;use ieee.std_logic_1164.all;entity mealy_2 isport ( reset : in std_logic; clock : in std

38、_logic; din : in std_logic; dout : out std_logic_vector( 2 downto 0 ) );end entity;architecture statemachine of mealy_2 is type state_type is ( s0, s1, s2, s3 ); signal presentstate : state_type; signal nextstate : state_type;begin process ( reset, clock ) - 更新当前状态 begin if reset = '1' then

39、presentstate <= s0; elsif rising_edge ( clock ) then presentstate <= nextstate; end if; end process; process ( presentstate, din ) - 生成次态 begin case presentstate is when s0 => if din ='1' then nextstate <= s1; else nextstate <= s0; end if; when s1 => if din ='1' the

40、n nextstate <= s2; else nextstate <= s1; end if; when s2 => if din ='1' then nextstate <= s3; else nextstate <= s2; end if; when s3 => if din = '1' then nextstate <= s0; else nextstate <= s1; end if; end case; end process; process ( presentstate, din ) - 输出 be

41、gin case presentstate is when s0 => if din = '0' then dout <= "000" else dout <= "001" end if; when s1 => if din = '0' then dout <= "010" else dout <= "011" end if; when s2 => if din = '0' then dout <= "100&