EDAx点阵滚动动画显示

1、四、课程设计的总体步骤1、单个字符的显示（如：黄）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signa

2、l i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1)begincase sel is when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if

3、;end process;sck<=clk1;end ;时序仿真：从图中可以看出，当clk1在第32个上升沿rck变为低电频，sck与clk1是同一电频，故此程序满足要求。 2、多个字符的跳动显示（如：黄小红）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture o

4、ne of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; cas

5、e lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0010"=> case sel is when others =>null; end case; when others=>null; end case; if clk1'event and clk1='1'then si

6、<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end process;sck<=clk1;end ; 时序仿真：从上图看出，当clk1在第32个上升沿rck变为低电频，sck与clk1是同一电频，故此程序满足要求。3、汉字的滚动和动画显示（如：黄小红+笑脸）：library ieee;use ieee.std_logic_1164.all;use ieee.std_

7、logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to

8、 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; case lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0

9、010"=> case sel is when others =>null; end case; when"0011"=> case sel is when others =>null; end case; when"0100"=> case sel is when others =>null; end case; when"0101"=> case sel is when others =>null; end case; when"0110"=> c

10、ase sel is when others =>null; end case; when"0111"=> case sel is when others =>null; end case; when"1000"=> case sel is when others =>null; end case; when"1001"=> case sel is when others =>null; end case; when"1010"=> case sel is when

11、others =>null; end case; when"1011"=> case sel is when others =>null; end case; when"1100"=> case sel is when others =>null; end case; when"1101"=> case sel is when others =>null; end case; when"1110"=> case sel is when others =>null

12、; end case; when"1111"=> case sel is when others =>null; end case;when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end

13、process;sck<=clk1;end ；时序仿真：从上图看出，当clk1在第32个上升沿rck变为低电频，sck与clk1是同一电频，si为输出电频，故此程序满足要求。五、结论与收获在三周的EDA课程设计过程中，我对VHDL语言有了更加深刻的认识。VHDL是超高速集成电路的硬件描述语言，它能够描述硬件的结构、行为与功能。另外，VHDL具有并发性，采用自上而下的结构式设计方法，适合大型设计工程的分工合作。在编写程序的时候，我才发现能看懂程序和能自己写程序是两个完全不同的概念，自己一开始写程序时，即便是一个很简单的功能模块，在编译时也可能产生很多错误，在不断的改错过程中，自己对VHDL语言的语法结构有了深刻的理解，对编译过程中常见的错误也有了全面的认识。通过这十三周的课程设计，我在熟悉了基于FPGA设计的同时，也学到了很多在学习课本知识时所体会不到的东西。完成此次设计后，我不仅能对Quartus II开发仿真软件熟练操作，能达到学以致用，同时还掌握了矩阵键盘和16×16点阵的工作原理。经过这一过程，我发现平常的学习在注重理论知识的掌握同时，要加强实验环节，只有通过不断