EDA交通灯控制器课程设计

1、交通灯控制器课程设计该交通信号控制器控制十字路甲、乙两条道路的红、黄和绿三色灯，指挥车辆和行人安全通行。 功能要求如下：1. 只有在小路上发现汽车时，高速公路上的交通灯才可能变成红灯。2. 当汽车行驶在小路上时，小路的交通灯保持为绿灯，但不能超过给定的时间。（20s）3. 高速公路灯转为绿色后，即使小路上有汽车出现，而高速公路上并无汽车，也将在给定的时间内保持绿灯。（60s）。高速公路通车小路有车 N N YT>60s Y5秒黄灯后小路通车 小路有车5s黄灯 NT>20s Y N Y设计如下：1hz分频器library ieee;use ieee.std_logic_1164.al

2、l;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen_pin1 isport(clk100hz:in std_logic; clk1hz:out std_logic);end fen_pin1;architecture bhv of fen_pin1 issignal qan:std_logic_vector(3 downto 0);signal qbn:std_logic_vector(3 downto 0);signal cin:std_logic;beginprocess(clk100hz)be

3、ginif(clk100hz'event and clk100hz='1')thenif qan="1001"then qan<="0000"cin<='1'else qan<=qan+1;cin<='0'end if;end if;end process;process(clk100hz,cin)beginif(clk100hz'event and clk100hz='1')thenif cin='1' thenif qbn=&quo

4、t;1001" then qbn<="0000"else qbn<=qbn+1;end if ;end if ;end if ;end process;process(qan,qbn)beginif (qan="1001"and qbn="1001")then clk1hz<='1'else clk1hz<='0'end if;end process;end bhv;2hz分频器library ieee;use ieee.std_logic_1164.all;entit

5、y fen_pin2 isport (clk100hz:in std_logic; clk2hz:out std_logic);end fen_pin2;architecture bhv of fen_pin2 isbeginprocess(clk100hz)variable cnt:integer range 0 to 24;variable tmp:std_logic;beginif(clk100hz'event and clk100hz='1')thenif cnt=24 thencnt:=0;tmp:=not tmp;elsecnt:=cnt+1;end if;

6、end if;clk2hz<=tmp;end process;end bhv;主干道控制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity contralz isport(clk:in std_logic; ra,ga,ya:out std_logic; timeah,timeal:out std_logic_vector(3 downto 0);end contralz;architecture bhv of contralz istype rg is(green,red,yel

7、low2);beginprocess(clk)variable a:std_logic;variable th,tl:std_logic_vector(3 downto 0);variable state:rg;beginif clk'event and clk='1'thencase state iswhen green=>if a='0'then th:="0101" tl:="1001" a:='1' ga<='1' ra<='0' ya<

8、;='0' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;elsetl:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'state:=red;end if;end if;when red=>if a='0'then th:="0001" tl:="1001&

9、quot; a:='1' ra<='1' ya<='0' ga<='0' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;elsetl:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'ra<='0'ga<='0

10、'state:=yellow2;end if;end if;when yellow2=>if a='0'then th:="0000" tl:="1001" a:='1' ya<='1' ga<='0' ra<='0' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;e

11、lsetl:=tl-1;end if;elseth:="0000"tl:="0000" ga<='0' ra<='0' ya<='0' a:='0'state:=green;end if;end if;end case;end if;timeah<=th;timeal<=tl;end process;end bhv;支路控制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.a

12、ll;entity contralx isport(clk:in std_logic; rb,gb,yb,chu:out std_logic; timeah,timeal:out std_logic_vector(3 downto 0);end contralx;architecture bhv of contralx istype rgy is(red,yellow1,green,yellow2);beginprocess(clk)variable a:std_logic;variable th,tl:std_logic_vector(3 downto 0);variable state:r

13、gy;beginif clk'event and clk='1'thencase state iswhen yellow1=>if a='0'then th:="0000" tl:="0100" a:='1' yb<='1' gb<='0' rb<='0' chu<='1' elseif not(th="0000"and tl="0001")thenif tl=&qu

14、ot;0000"thentl:="1001"th:=th-1;elsetl:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'state:=green;end if;end if;when green=>if a='0'then th:="0001" tl:="1001" a:='1' gb<='1' rb<='0' yb<='0'

15、 chu<='1' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;elsetl:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'state:=yellow2;end if;end if;when red=>if a='0'then th:="0101" tl:=

16、"0100" a:='1' rb<='1' yb<='0' chu<='1' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;elsetl:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'state:=yellow1;end

17、if;end if;when yellow2=>if a='0'then th:="0000" tl:="0100" a:='1' yb<='1' gb<='0' rb<='0' chu<='1' elseif not(th="0000"and tl="0001")thenif tl="0000"thentl:="1001"th:=th-1;elset

18、l:=tl-1;end if;elseth:="0000"tl:="0000"a:='0'chu<='0'state:=red;end if;end if;end case;end if;timeah<=th;timeal<=tl;end process;end bhv;反馈器library ieee;use ieee.std_logic_1164.all;entity smen is port( sm ,re,gr,ye:in std_logic; jinji:out std_logic);end sm

19、en;architecture se of smen isbeginprocess isbeginif(sm='1' and re='0' and gr='0' and ye='0') then jinji<='1'else jinji<='0'end if;end process;end se;消抖电路library ieee;use ieee.std_logic_1164.all;entity xiaodou isport(jinji,clk1hz:in std_logic; b:o

20、ut std_logic);end xiaodou;architecture bhv of xiaodou issignal temp1:std_logic;beginprocess(clk1hz,jinji)variable temp2:std_logic;beginif(clk1hz'event and clk1hz='0')thentemp1<=jinji;temp2:=not temp1;end if;b<=temp1 and temp2 and clk1hz;end process;end bhv;状态转换library ieee;use ieee

21、.std_logic_1164.all;entity no isport(a:in std_logic; en:out std_logic);end no;architecture no_arc of no isbeginprocess(a)variable tmp:std_logic;beginif(a'event and a='1')thentmp:=not tmp;end if;en<=tmp;end process;end no_arc;mux4llibrary ieee;use ieee.std_logic_1164.all;entity mux41 i

22、sport(sel:in std_logic_vector(2 downto 0);d0,d1,d2,d3:in std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0);so:out std_logic_vector(1 downto 0);end mux41;architecture bhv of mux41 isbeginprocess(sel)begincase sel iswhen"100"=>q<=d2;so<="00"when"101"

23、;=>q<=d3;so<="01"when"000"=>q<=d0;so<="10"when others=>q<=d1;so<="11"end case;end process;end bhv;译码器library ieee;use ieee.std_logic_1164.all;entity dec7s isport(d:in std_logic_vector(3 downto 0);q0,q1,q2,q3,q4,q5,q6:out std_logic);end dec7s;architecture bhv of dec7s isbeginprocess(d)variable q:std_logic