FPGA实验报告

1、FPGA 实验上机报告实验二1. Part1 代码LIBRARY ieee;ENTITY part1 ISPORT(SW:INLEDR :OUTSTD_LOGIC_VECTOR(17 DOWNTO 0);STD_LOGIC_VECTOR(17 DOWNTO 0);END part1;ARCHITECTURE Behavior OF part1 ISBEGINLEDR=SW;END Behavior;运行结果：拨码开关控制LED 闪亮2. Nice 代码LIBRARY ieee;ENTITY nice IS PORT(SW :IN HEX0 :OUT LEDR :OUTSTD_LOGIC_VEC

2、TOR(0 TO 17);STD_LOGIC_VECTOR(0 TO 6);STD_LOGIC_VECTOR(0 TO 17);END nice;ARCHITECTURE Behavior OF nice ISSIGNAL temp :STD_LOGIC_VECTOR(0 TO 3);BEGINLEDR=SW;temp(3)=SW(0);temp(2)=SW(1);temp(1)=SW(2);temp(0)HEX0HEX0HEX0HEX0HEX0HEX0HEX0HEX0HEX0HEX0HEX0=1001000;END CASE;END PROCESS;END Behavior;运行结果：拨码开

3、关控制数码管显示数字3.数字时钟电路代码（ 1） watch.vhd：LIBRARY IEEE;-This is a simple watch with sec/min/hour display in DE2 broad-SW(0) is the reset input, when SW(0)=1,the program runs.ENTITY watch ISPORT(SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0);clk_50:IN STD_LOGIC;HEX0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX1:OUT STD_LOGIC

4、_VECTOR(6 DOWNTO 0);HEX2:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX5:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX6:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);HEX7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END watch;-ARCHITECTURE rtl OF watch ISCOMPONENT sec

5、_clk IS-create a clk signal 1Hz frequencyPORT(clk_50 :IN STD_LOGIC;clk_div1 :OUT STD_LOGIC);END COMPONENT;COMPONENT count4 IS-second counterPORT(res,stop,clk :IN STD_LOGIC;ca :OUT STD_LOGIC; -ca=1 when second count=59 a :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT;COMPONENT count3 IS-second coun

6、terPORT(res,clk :IN STD_LOGIC;ca :OUT STD_LOGIC;-ca=1 when second count=59a:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT seccount IS-second counterPORT(res,clk :IN STD_LOGIC;ca :OUT STD_LOGIC;-ca=1 when second count=59a,b :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT mincount

7、 ISPORT(en,res,clk:IN STD_LOGIC;ca:OUT STD_LOGIC;a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT count24 ISPORT(en,res,clk:IN STD_LOGIC;a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT dis ISPORT(d:IN STD_LOGIC_VECTOR(3 DOWNTO 0);q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPON

8、ENT;SIGNAL stop: STD_LOGIC:=0;SIGNAL res: STD_LOGIC:=0;SIGNAL sec1: STD_LOGIC:=0;SIGNAL t1: STD_LOGIC:=0;SIGNAL m1: STD_LOGIC:=0;SIGNAL sec_c: STD_LOGIC:=0;SIGNAL min_c: STD_LOGIC:=0;SIGNAL m_a: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL t_a: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL sec_a: STD_LOGIC

9、_VECTOR(3 DOWNTO 0):=0000;SIGNAL sec_b: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL min_a: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL min_b: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL hour_a: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;SIGNAL hour_b: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;BEGINres=SW(0);stop=SW(1);u

10、1: sec_clk PORT MAP(clk_50, m1);u2: count4 PORT MAP(res, stop,m1,t1,m_a);u3: count3 PORT MAP(res, t1,sec1,t_a);u4: seccount PORT MAP(res, sec1,sec_c,sec_a, sec_b);u5: mincount PORT MAP(sec_c,res,sec1,min_c, min_a, min_b);u6: count24 PORT MAP(min_c, res,sec1,hour_a, hour_b);u7: dis PORT MAP(m_a,HEX0)

11、;u8: dis PORT MAP(t_a,HEX1);u9: dis PORT MAP(sec_a,HEX2);u10: dis PORT MAP(sec_b,HEX3);u11: dis PORT MAP(min_a,HEX4);u12: dis PORT MAP(min_b,HEX5);u13: dis PORT MAP(hour_a,HEX6);u14:dis PORT MAP(hour_b,HEX7);END rtl;(2)Sec_clk.vhd:LIBRARYIEEE;USEUSEENTITY sec_clk ISPORT(CLK_50: IN STD_LOGIC;clk_div1

12、: OUT STD_LOGIC);END ENTITY sec_clk;ARCHITECTURE rtl OF sec_clk ISSIGNALcount:STD_LOGIC_VECTOR(21DOWNTOBEGINPROCESS(CLK_50)BEGINIF(CLK_50event AND CLK_50=1) THENcount0);-33554432ELSEcount=count+1;END IF;END IF;END PROCESS;clk_div1= count(21);-67108864END ARCHITECTURE rtl;(3)seccount.vhd:LIBRARY IEEE

13、;ENTITY seccount ISPORT(res,clk:IN STD_LOGIC;ca:OUT STD_LOGIC;a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END seccount;ARCHITECTURE rtl OF seccount ISSIGNAL aout,bout: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL cout:STD_LOGIC;BEGINPROCESS(clk,res)BEGINIF (res=0) THENaout=0000;bout=0000;- cout=0;aout=0000;IF (bout

14、=0101) THENbout=0000;- cout=1;ELSE bout=bout+1;aout=aout+1;bout=bout;- cout=0;END IF;END IF;END PROCESS;PROCESS(clk,aout,bout)BEGINIF clkevent and clk=1 THENIF bout=0101 and aout=1001 THENcout=1;ELSEcout=0;END IF;END IF;END PROCESS;a=aout;b=bout;ca=cout;END rtl;（ 4） midcount.vhd：LIBRARY IEEE;ENTITY

15、mincount ISPORT(en,res,clk:IN STD_LOGIC;ca:OUT STD_LOGIC;a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END mincount;ARCHITECTURE rtl of mincount ISSIGNAL aout,bout: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL cout: STD_LOGIC;BEGINPROCESS(en,clk,res)BEGINIF (res=0) THENaout=0000;bout=0000;cout4)THENIF(aout8)THENaout=

16、0001;bout=0000;cout=1;ELSEaout=aout+1;END IF;ELSEIF(aout=9)THENaout=0000;bout=bout+1;ELSEaout=aout+1;cout=0;END IF;END IF;END IF;END IF;END PROCESS;a=aout;b=bout;ca=cout;END rtl;（ 5） count24.vhd：LIBRARY IEEE;ENTITY count24 ISPORT(en,res,clk:IN STD_LOGIC;a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHI

17、TECTURE rtl of count24 isSIGNAL aout,bout: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(en,clk,res)BEGINIF(res=0)THENaout=0000;bout1)THENIF(aout2)THENaout=0000;bout=0000;ELSEaout=aout+1;END IF;ELSEIF(aout=9)THENaout=0000;bout=bout+1;ELSEaout=aout+1;END IF;END IF;END IF;END IF;END PROCESS;a=aout;bqqqqqq

18、qqqq=0010000;END CASE;END PROCESS;END rtl;(7)count3:LIBRARY IEEE;ENTITY count3 ISPORT(res,clk:IN STD_LOGIC;ca:OUT STD_LOGIC;a:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count3;ARCHITECTURE rtl OF count3 ISSIGNAL aout: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL cout:STD_LOGIC;BEGINPROCESS(clk,res)BEGINIF (res=0) THENaout=0000;- cout=0;aout=0000;- cout=1;ELSE aout=aout+1;- cout=0;END IF;END IF;END PROCESS;PROCESS(clk,aout)BEGINIF clkevent and clk=1 THENIF aout=1001