在高边工作的MOSFET其可能的失效模式和失效现象

1、Power MOSFET in High-Side Operating Modes, Possible Failure Modes, and Failure Signatures+ E+ X  n4 n& k+ y, z. ! Z3 z: M& nPower MOSFETs in high-side application can fail under any one of the following modes of operation:(a) High-impedance gate drive(b) Electro-static discharge (E

2、SD) exposure2 B3 b- b5 D, G+ p+ D- f(c) Electrical over-stressed (EOS) operation9 k/ ' 4 l! f7 ! jIn most cases, failure analysis of the damaged MOSFET reveals a signature that can point towards a possible cause of failure.(a) High-Impedance Gate Drive4 f9 C/ ; b6 _A generic schematic configurat

3、ion for a high-side driver with inductive load is shown in figure 1. A typical gate drive design based on an application-specific integrated circuit (ASIC) caters to the primary gate charge requirements of the MOSFET, which are on the order of a few tens to hundreds of nanocoulombs. An effort to ach

4、ieve high efficiency and optimize the integration of the ASIC results in low-current (< 50 A) gate drives (V2 referenced to power supply ground) with a high output impedance (> 1 M). This basically satisfies the total gate-charge requirements of the MOSFET.However, to avoid overloading the ASI

5、C, the external gate resistor (R2) in such a design tends to have a high ohmic value (ranging from tens of ohms to several kiloohms). The feedback resistor (R3) also usually has a high ohmic value (ranging from several kiloohms to 1 M). As a result, the source (S) of the power MOSFET (U1) is virtual

6、ly floating.% Z; S' E' x  3 C! j, y. R) b  E( sThe effect is magnified during turn-off and recirculation of the energy stored in the inductor (L1). & Y2 ' V8 c6 G# v! P9 E9 _  o" P9 3 J* L * w2 1 H! y( , v; f* M# R0 N. H) Fig. 1 - Typical High

7、Side DriverThis approach fully satisfies the requirements for steady-state operation, where small amount of current, on the order of a few microamps, is all that is required to maintain the on state. But it can be inadequate for dynamic (transient) turn-on and turn-off operation of MOSFET. In this l

8、atter case, the MOSFET switching operation can easily occur in linear mode, which is an unstable and non-characterized area of MOSFET operation (figure 2). Fig. 2 - Floating Source and Slow Turn-OffDuring turn-on and turn-off, switching power losses are likely to dissipate from a very small are

9、a of the active die. The resulting failure signature is high-power burn-out, with a random amount of damage located in the active area of the die. Invariably such failure is labeled as EOS.9 d( i+ L5 p$ . _2 k$ g; fAnother subtle failure evidenced during the analysis of the failed MOSFET (with a vir

10、tually floating gate circuit configuration) is in the gate-source area. A DC parameter test of the gate-source area shows out of spec readings. The failure mode is subtle insofar as the leaky device recovers even during the DC parameter test. This failure mode remains under investigation to obtain a

11、 full explanation.A failure example of a DPAK power MOSFET is shown in the figures 3, 4, and 5.3 7 T% ( j  q5 N; U5 A% T5 e/ d5 Z7 T6 A% J  T" / s& % ; B Fig. 3 - EOS Damage Location Fig. 4 - Damage on BPSG: B' . g: s" r2 B3 8 M1 D6 _, q( / Z: M -

12、 c* |4 i5 S7 UFig. 5 - Damage on Gate Poly  o/ A9 ) m& T* B. x; P' F(b) Electro-Static Discharge (ESD) Exposures& p/ f0 u8 , F& s& dA second possible scenario arising from a virtually floating gate condition caused by the high impedance of an ASIC driver and/or high gat

13、e resistor is increased susceptibility of the gate-source area for damage from ESD or a similar event. In addition to a typical ESD event, high-energy, high-voltage transients of short duration can be generated from energy re-circulation and/or energy interruption frominductive components. With refe

14、rence to figure 6, these include the low-side load (L1, R1), other parallel connected load (L2, R4), and series feed-in/harness impedance (L3, R5)." e3 r* F4 p1 q/ 3 |; p1 M) y; i, |  P. J6 z  R Fig. 6 - L1, L2, L3 Sources of Transients2 a7 u4 i6 3 j" T8 r7 D* 2 JF

15、ailure signatures are usually located near the gate termination and in the gate-source area. An example of a DPAK power MOSFET failure is shown in figures 7, 8 and 9.8 # I5 X, ?+ w) O1 Q Fig. 7 - ESD Damage near the Gate-Source9 H# |* _# i  ?! I. a6 I7 k7 o3 B# Z# W. G* s  O

16、0 r9 J! _ : r( U+ |% t, x5 P' IFig. 8 - ESD on the Gate Termination & ?- P1 f3 |2 ?" t# C" fFig. 9 - Close-up of ESD Damage( i' g5 C, V! D. x(c) Electrical Over Stressed (EOS) Operation + y# O# x: g- C6 l% NHigh-energy or high-voltage short-duration transients ap

17、pearing on the drain-source termination of the MOSFET (figure 6) can result in damage with a variety of signatures.- j* L7 u! B& 9 _/ zTransients that are faster than the breakdown time of the body diode may produce punctures anywhere in the active area of the drain-source. Such punctures have t

18、he appearance of a pin-hole at the damage site. They may be attributed to an ESD event or an ESD-like event arising from other circuit components or parasitics.+ T$ P8 E$ i" $ y. : W  BWhere energy/voltage values are not too high but of a sufficient duration to break down the body dio

19、de, avalanche results. Avalanche results in extensive damage and in fact destroys the evidence that failure analysis would need to determine the root cause. These are true EOS events.EOS can also result from a mismatch of thermal management and continuous power dissipation in the device, even when t

20、he device is fully turned on. When heat-sinking is inadequate, heat can build up in the junction during continuous operation. Eventually a thermal runaway occurs. The device is completely destroyed and also classified as an EOS. E9 5 g9 N, + t: K8 ; s" l( N3 C/ eD2PAK example: figures 10 to 12

21、are failure signatures for a D2PAK power MOSFET. Fig. 10 - High Power EOS (after Decapsulation)4 v4 o. e, c'  # a; ?4 d9 r9 m5 u( d7 P8 bFig. 11 - EOS Signature after Removing Top Metal Layer / 2 M9 T- : ?, D0 _0 n1 E1 G8 Fig. 12 - EOS Damage at 50 x MagnificationSO-8 dual example

22、: figures 13 to 15 are another example of a dual SO-8 power MOSFET failure identified as EOS% I, I9 D; O5 t! W8 G! L # F0 M* H, l: |0 b$ ) HFig. 13 - Failure near Bond Wire : D- h6 T% x! $ y7 p8 p0 EFig. 14 - EOS in Active Region8 k# u" & x% h % E8 d% 5 M& k/ _% cFig. 15 - Close-up of EOS Damage. Q8 s, z( T% n- f, / O- n: A9 k! s' d8 w! q$ v6 y0 b2 t! m" u) O" jSUMMARY& g# K4