eda课程设计报告(2)

1、.正文一、设计思路1.基于QUASTUS II平台，利用DDS（直接数字信号合成）技术，采用VHDL语言，设计一波形信号发生器。首先根据对各波形的幅度进行采样，获得各波形的波形数据表，然后FPGA根据输入的时钟（频率可根据要求可变）作为地址信号，从FPGA数据线上输出相应的波形数据，再送入实验板上的D/A转换芯片进行转换为模拟信号，最后送入滤波电路滤波后输出。2.实验整体框图如下：由斜降锯齿波模块（dj）、斜升锯齿波模块（dz）、方波模块（fb）、三角波模块（jcb）、阶梯波模块（jtb）、6选1选择器（xz）正弦波模块（zx）以及、译码显示模块（ym）组成。二、设计输入文件与调试；1.分频器

2、 用4个100分频器串接实现。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity fenpin isport (clk: in std_logic; clkfen: out std_logic); end fenpin;architecture fenpin of fenpin issignal clk_mid: std_logic;begin process(clk) variable data:integer range 0 to 99; begin if clkevent and

3、 clk=1 then if data=99 then data:=0; clk_mid=not clk_mid; else data:=data+1;end if;nd if;clkfen=clk_mid;end process;end fenpin;2.递减（锯齿波）波形数据产生模块设计采用2550循环加法计数器实现。设计思路是: reset 是复位信号, 要首先考虑。tmp 是引进的一个中间变量。通过赋值给输出值。clk 是时钟信号, 当复位信号有效时, 输出为1, 输出最大值设为“255”,最小值设为“0”,从“0”开始, 当时钟检测到有上升沿的时候, 输出就会呈现递减的趋势, 减“1

4、”。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY dj IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END dj;ARCHITECTURE behave OF dj ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset=0THEN tmp:=11111111; E

5、LSIF clkEVENT AND clk=1THEN IF tmp=00000000THEN Tmp:=11111111; ELSE tmp:=tmp-1; END IF;END IF; q=tmp; END PROCESS;END behave;3.递增（锯齿波）波形数据产生模块设计采用0255 循环加法计数器实现。与递减相反。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY dz IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC

6、_VECTOR (7 DOWNTO 0);END dz;ARCHITECTURE behave OF dz ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset=0THEN tmp:=00000000; ELSIF clkEVENT AND clk=1THEN IF tmp=11111111THEN tmp:=00000000; ELSE tmp:=tmp+1; END IF; END IF;q=tmp; END PROCESS;END behave;4.方波波形数据产生模

7、块设计采用高/ 低电平实现, 用cnt 来控制方波的周期, 用a 的值来控制输出到底是高电平还是低电平。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;ENTITY fb IS PORT (clk,reset: IN STD_LOGIC; q:OUT INTEGER RANGE 0 TO 255);END fb; ARCHITECTURE behave OF fb ISSIGNAL a: BIT;BEGIN PROCESS (clk,reset) VARIABLE cnt: INTEGER range 0 to 31; BEGIN IF reset=0THE

8、N A=0; ELSIF clkEVENT AND clk=1THEN IF cnt31 THENCnt:=cnt+1; ELSE cnt:=0; a=NOT a;END IF; END IF; END PROCESS; Process (clk,a) BEGINIF clkEVENT AND clk=1THEN IF a=1THEN Q=255; ELSE Q=0; END IF; END IF;END PROCESS;END behave;5.三角波波形数据产生模块设计采用02550 循环加/ 减法计数器实现。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.AL

9、L;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jcb IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END jcb;ARCHITECTURE behave OF jcb ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE a: STD_LOGIC; BEGIN IF reset=0THEN tmp:=00000000; ELSIF clkEVENT AND

10、 clk=1THEN IF a=0THENIF tmp=11111110THEN tmp:=11111111; a:=1; ELSE tmp:=tmp+1; END IF;ELSE IF tmp=00000001THEN tmp:=00000000; a:=0;ELSE tmp:=tmp-1; END IF; END IF;END IF;q=tmp; END PROCESS;END behave6.阶梯波形数据产生模块设计可采用八进制计数器实现, 每次阶梯常数为32 。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_uns

11、igned.all;entity jtb isport(clk,reset:in std_logic;q:out std_logic_vector(7 downto 0);end jtb;architecture a of jtb isbeginprocess(clk,reset)variable tmp:std_logic_vector(7 downto 0);beginif reset=0 thentmp:=00000000;else if clkevent and clk=1 thenif tmp=11111111 thentmp:=00000000;elsetmp:=tmp+16;en

12、d if;end if;end if;q=tmp;end process;end a;7.正弦波波形数据产生模块设计采用描点法来描述正弦波,在仿真波形中可以看到输入输出引脚设置, 其中clk 输入时钟端口, reset 为输入复位端口, d 为整数输出端口, 一个周期选取64 个点, 计算出64 个常数后, 查表输出5 。复位信号的级别高于其它信号, 而且低电平是有效电平, 所以整个程序的工作状态应处于高电平状态。当时钟检测到上升沿时,计数器计数, 描点工作开始。没达到最大值之前,一直自加, 否则就自动转为“0”。那么首先要确定这64 个点。然后在程序里用case 语句来择。library i

13、eee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zx is port(clk:in std_logic; reset:in std_logic; q:out std_logic_vector(7 downto 0);end zx;architecture behav of zx is signal b:integer range 0 to 63; signal d:integer range 0 to 255;beginprocess(clk)

14、begin if reset=0then b=0; elsif clkevent and clk=1 then if b=63 then b=0; else bddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddnull; end case; end process; qqqqqqqNULL; END CASE; END PROCESS; END behave; 9译码library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.s

15、td_logic_unsigned.all;entity ym is port( clk,rst :in std_logic; data :in std_logic_vector(7 downto 0); sel :out std_logic_vector(2 downto 0); data_disp:out std_logic_vector(6 downto 0);end ym;architecture RTL of ym issignal count :integer range 9 downto 0;signal temp :integer range 4 downto 0;signal

16、 number_h,number_t,number_l:integer range 0 to 9;begin process(data,clk,rst)beginif(rst=0)then number_h=0; number_t=0; number_l=200 AND to_integer(unsigned(data)-200=50)then number_h=2; number_t=5; number_l=200 AND to_integer(unsigned(data)-200=40)then number_h=2; number_t=4; number_l=200 AND to_int

17、eger(unsigned(data)-200=30)then number_h=2; number_t=3; number_l=200 AND to_integer(unsigned(data)-200=20)then number_h=2; number_t=2; number_l=200 AND to_integer(unsigned(data)-200=10)then number_h=2; number_t=1; number_l=200)then number_h=2; number_t=0; number_l=100 AND to_integer(unsigned(data)-1

18、00=90)then number_h=1; number_t=9; number_l=100 AND to_integer(unsigned(data)-100=80)then number_h=1; number_t=8; number_l=100 AND to_integer(unsigned(data)-100=70)then number_h=1; number_t=7; number_l=100 AND to_integer(unsigned(data)-100=60)then number_h=1; number_t=6; number_l=100 AND to_integer(

19、unsigned(data)-100=50)then number_h=1; number_t=5; number_l=100 AND to_integer(unsigned(data)-100=40)then number_h=1; number_t=4; number_l=100 AND to_integer(unsigned(data)-100=30)then number_h=1; number_t=3; number_l=100 AND to_integer(unsigned(data)-100=20)then number_h=1; number_t=2; number_l=100

20、 AND to_integer(unsigned(data)-100=10)then number_h=1; number_t=1; number_l=100)then number_h=1; number_t=0; number_l=90)then number_h=0; number_t=9; number_l=80)then number_h=0; number_t=8; number_l=70)then number_h=0; number_t=7; number_l=60)then number_h=0; number_t=6; number_l=50)then number_h=0

21、; number_t=5; number_l=40)then number_h=0; number_t=4; number_l=30)then number_h=0; number_t=3; number_l=20)then number_h=0; number_t=2; number_l=10)then number_h=0; number_t=1; number_l=to_integer(unsigned(data)-10;elsenumber_h=0;number_t=0;number_l=to_integer(unsigned(data);end if;end process;proc

22、ess( clk,rst,temp,number_h,number_l) begin if(clkevent and clk=1)then if(temp=2)then temp=0; else tempsel=001; countsel=010; countsel=100; countNULL; end case;end process;process(count)begin case count iswhen 0=data_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispnull;end case;end process;end RTL;1.递减锯齿波仿真结果三、仿真与验证结果2.递增锯齿波仿真结果3.方波仿真结果4.阶梯波仿真结果5、三角波仿真结果6.正弦波仿真结果四、设计结论运用VHDL 语言进行智能函数发生器功能的设计具有以下优势: 信号发生器的功能测试与仿真实验结果表明, 时序和波形正确, 达到了设计的功能要求