电子钟课程设计报告数字钟设计

1、题目：数字钟设计一、实验目的学习并掌握数字钟的原理、设计方法。二、实验内容计数时钟由模60秒计数器、模60分计数器、模24小时计数器、报时模块、分、时校定模块及输出显示模块构成。可以采用同步计数器或异步计数器设计方法。三、实验要求1. 计时范围为0小时0分0秒至23小时59分59秒2. 采用6个8段数码管分别显示小时十位，小时个位、分钟十位、分钟个位、秒十位、秒个位。3. 整点报时，蜂鸣器响5声，每秒1声。4. 校时功能，能够单独校分、校时。用按键控制。5. 具有清零、启动/停止计数的功能。用按键控制。四、实验原理数字钟的基本原理是采用时钟源提供的频率作为秒模块的时钟进行计数，当秒模块计数达到

2、59秒时为分模块提供时钟，该时钟通过状态选择模块送到分模块，同理，分模块向小时模块提供时钟时也是如此。整点报时模块是利用分钟向小时的进位时钟脉冲作为触发源，利用秒的个位计时以及实验板提供的时钟源频率达到报时五秒的目的。译码显示模块则通过8421BCD码与数码管各段的关系进行转化，由于实验板不支持动态扫描所以需在秒，分，时的个位与十位都添加译码显示模块。原理框图如下： 时钟源秒模块分模块状态选择模块时模块状态选择模块暂停信号调分模块块数码管数码管数码管报时模块 五、模块设计1、 秒计数模块library ieee;use ieee.std_logic_1164.all;use ieee.std_

3、logic_unsigned.all;entity second is port(clk,rst:in std_logic; enmin:out std_logic; shiwei:out std_logic_vector(3 downto 0); gewei:out std_logic_vector(3 downto 0);end entity second;architecture rtl of second issignal a,b:std_logic_vector(3 downto 0);signal c:std_logic_vector(7 downto 0); begin c<

4、;=b&a; process(clk,rst,c) begin if(rst='1')then a<="0000" b<="0000" enmin<='0' elsif(clk'event and clk='1')then a<=a+1; if(a="1001")then a<="0000" b<=b+1; if(b="0101")then b<="0000" end i

5、f; end if; end if; case c is when "01011001"=>enmin<='1' when others=>enmin<=null; end case; end process; gewei<=a; shiwei<=b;end architecture rtl;其模块仿真图为： 2、 分计数模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute is port(clk,r

6、st:in std_logic; enhour:out std_logic; mshiwei:out std_logic_vector(3 downto 0); mgewei:out std_logic_vector(3 downto 0);end entity minute;architecture rtl of minute issignal m,n:std_logic_vector(3 downto 0);signal c:std_logic_vector(7 downto 0); begin c<=n&m; process(clk,rst,c) begin if(rst=

7、'1')then m<="0000" n<="0000" enhour<='0' elsif(clk'event and clk='1')then m<=m+1; if(m="1001")then m<="0000" n<=n+1; end if; end if; if(c="01011001")then n<="0000" m<="0000" end

8、if; case c is when "01011001"=>enhour<='1' when others=>enhour<=null; end case; end process; mgewei<=m; mshiwei<=n;end architecture rtl;其模块仿真图为： 3、 时计数模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour is port(clk,rst:in std_log

9、ic; hshiwei:out std_logic_vector(3 downto 0); hgewei:out std_logic_vector(3 downto 0);end entity hour;architecture rtl of hour issignal p,q:std_logic_vector(3 downto 0); begin process(clk,rst) begin if(rst='1')then p<="0000" q<="0000" elsif(clk'event and clk=

10、9;1')then p<=p+1; if(p="1001")then p<="0000" q<=q+1; end if; end if; if(q="0010" and p="0100")then p<="0000" q<="0000" end if; end process; hgewei<=p; hshiwei<=q;end architecture rtl; 其模块仿真图为： 4、 状态选择模块library ieee;

11、use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity set isport(sel:in std_logic; clk:in std_logic; key:in std_logic; y:out std_logic);end entity set;architecture rtl of set issignal a:std_logic;beginprocess(sel)is begincase sel is when '0'=>a<=clk; when '1'=>a

12、<=key; when others=>a<=clk; end case;y<=a;end process;end architecture rtl;其模块仿真图为： 5、 整点报时模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alert is port(clk:in std_logic; d:in std_logic_vector(3 downto 0); en:in std_logic; alarm:out std_logic);end entity

13、 alert;architecture rtl of alert is signal enalarm:std_logic; begin alarm<=enalarm; process(clk,en,d) begin if(en='1')then enalarm<=clk; end if; if(d="0101")then enalarm<='0' end if; end process;end architecture rtl;其模块仿真图为： 6、 译码显示模块library ieee;use ieee.std_logic

14、_1164.all;use ieee.std_logic_unsigned.all;entity deled isport(num: in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0);end entity deled;architecture rtl of deled isbegin led<="1111110"when num="0000"else "0110000"when num="0001"else "

15、1101101"when num="0010"else "1111001"when num="0011"else "0110011"when num="0100"else "1011011"when num="0101"else "1011111"when num="0110"else "1110000"when num="0111"else "111111

16、1"when num="1000"else "1111011"when num="1001"else "1110111"when num="1010"else "0011111"when num="1011"else "1001110"when num="1100"else "0111101"when num="1101"else "1001111"when num="1110"else "1000111