计算机架构说明.

1、1BY Louis Cao 07/17/2012ELEMENTARY GUIDELINE 2BY Louis Cao 07/17/2012 Black diagram ContentBase diagram Power summary System Architecture Power diagram Beforehand power on M/BFrom power boardAdapter sense circuitFirst reset signal ACPI states supported RSMRST#_3 to ICH3Enable DC/DC circuitry CPU mas

2、ter power Power good signal Clock summaryBase diagram of origin Clock origin SMbus Architecture3BY Louis Cao 07/17/2012Block diagramHomeSMSMS SC CU25CPUC114A033 QGX6 QSINTEL01D114F018S 0253U525Almador-MU11intel.U518ICH3intelBIOSintel.U8U32VRAMU8VRAMU9PSBHub interfaceLPC busPCI busAGP busMINI_PCIUSB

3、PortsHDD CDLANKeyboardInfraredTouchpadPS/2SerialParallelFloppyESSU529PCIbus1.8V,66MHz1.2V,133MHz1.5V,66MHz3.3V,33MHz3.3V,33MHz3.3V,133MHz4BY Louis Cao 07/17/2012Almador-MGMCH3 - MMobile Tualitin / Coppermine-TProcessorSO-DIMM 1SO-DIMM 2ICH3-M(I/O Controller Hub)Mini PCIType 2Modem/NICATI P6Docking C

4、onnector+3.3V PCI Bus (33 MHz)CardBusControllerPCI1420208 TQFPCardBus Slot 0CardBus Slot 1PSB - 1.2V, 133 MHzHDD (ATA 66/100) MultiBay OptionsPrimary IDECNTRLSecondary IDECNTRL421 BGA625 BGASIO(Kahuna)208 TQFPLPC Bus1.5V AGP Bus - 4XSDRAM 3.3V, 133 MHzUSB 1USB 2Legacy Ports:Parallel, Serial,PS2 / Mo

5、useFWH 4 or 8Mb(Firmware Hub)PLCC32BluetoothSystem Memory1.0 GB MaxAC97CNTRLBattery2Multi-bayBattery1DC/DCAC ADPTR+3.3V+5V+1.8V+1.5V+VCCP - CPU COREVCC+3VCC+12VPort 0Port 1Port 2Port 3479 uFCPGA+1.2V - CPUIO/GTL PUsLANCNTRLCK TitanClock ChipESS1988 AllegroAudioController / EQ-Pwr AmpMemoryCRT/*DVIPa

6、nel / DDC ?USB 3Port 4Port 5*FloppyBiometricsInternal ConnectorFast IRMemoryQ-SwitchArcade DockingZoom Video?Q-Switch512 MB Max512 MB Max484 BGA2Mx322Mx32*Battery3 CD,CD R/W,DVD,HDD, FDD,ZIP,Batt,LS260*Kinnereth+*Magnetics*Jumper*RJ45DOCKTV OutSystem ArchitectureHome5BY Louis Cao 07/17/2012SODIMM1SO

7、DIMM2SM BUS ArchitectureHomeU518ICH3intelSMSMS SC CU25ICH_SMDAT_3ICH_SMCLK_3SODIMM1_3SODIMM2_3SM_ICHDATA0SM_ICHDATA1SM_ICHCLK0SM_ICHCLK1U504P.11P.11P.126BY Louis Cao 07/17/2012BATTERYDOCKINGEEPROMTHERMALSM BUS ArchitectureHomeSMSMS SC CU25SMB_CLKSMB_DATASDA_5DSCL_5DI2C_DCKENSMSMS SC CU25P.20P.39P.19

8、U526P.34SDA1_5SCL1_5P.35P.40P.197BY Louis Cao 07/17/2012Power summaryHome+VADPTR+VADPTR_SW+VBAT+VADPTR_IO+VADPTR_SW_IO+VBAT_IOIO/B+VAGTLREF+V12 , +V5 , +V5ALWAYS , +V3ALWAYS , +PVBAT , +V1.8ALWAYS+V_RTC , +V3A_ICH , +3VAUX+V3S , V3 _ICHLAN , +V3+V3_LAN+3V_MP_PWR+VS_SMREFRTCBAT+V1.8A_ICH+V1.8_ICHLAN

9、+V1.8SVS_HUBREF , +VS_HUBVSWINGVDD_CORE1.8 , VDD_PLL1.8VDD_PNLIO1.8 , VDD_PNLPLL1.8VDD_DAC1.8 , VDD_MEMPLL1.8+V1.5S+V1.5S_ICH+VS_COMSREF+V1.5AT1AGPAGPREF+4VS+3VREGUSBVCC1 +V4.8S_A , +V5SFWH_VPP+V3S_MSIO+V3A_MSIO+V2.5SVDD_DAC2.5+VGA_V3SVDDR_MEM2.5VREFV5SHDDV5S_MB+V5S_KHREFACARDVPPBCARDVPPACARDVCCBCAR

10、DVCC+VTT , +VCC +3V_L_LAN8BY Louis Cao 07/17/2012Beforehand Power in M/BHome(1) FROM IO/B : +VADPTR , +VADPTR_SW , +VBAT FROM P/B : +V12 , +V5ALWAYS , +V3ALWAYS (2) OTHER : +PVBAT , +V1.8ALWAYS , +V3A_ICH , +1.8A_ICH , +V_RTC +V1.8_ICHLAN , V3_ICHLAN +3VAUX +V3_LAN , +V3_L_LAN WAKE UP FROM LANWAKE U

11、P FROM MODEM+V5ALWAYS+V1.8ALWAYS+V3ALWAYS+VBAT+VPBAT+V1.8A_ICH , +V1.8_ICHLAN+V3A_ICH , V3_ICHLAN , +V3_LAN+V3_L_LAN , +3VAUX , +V_RTCSupply Logic circuit power9BY Louis Cao 07/17/2012From Power/BoardHomeCD_JACK+VADPTR_IOIO/BL1002Q1000D1002+VADPTR_SW_IO+VBAT_IOP.50CN1003 CN504M/BP.41CN509+VBAT+VADPT

12、R_SW+V5ALWAYSCN510+V3ALWAYS+V5+V12PGOOD1SLP_S5#_3RV3AONPOWER12345672+VADPTR+VADPTR_SW+VBAT+VADPTR_IO+VADPTR_SW_IO+VBAT_IOIO/B10BY Louis Cao 07/17/2012ADAPTER SENSE CIRCUITHomeU1000LM2601MBAT_IO+VADPTR_IOBACKFEED_IODISCONNECT_IOACPRES_3_IODCPRES_3_IOADPTR_EN_3_IOR1011,R1007Q1001,R1013P.50(1) MBAT_IO

13、: denote which in the system is supply or being charged(4) ACPRES_3_IO : High when +VADPTR_IO 17Volts(3) DCPRES_3_IO : High when 12Volts +VADPTR_IO 2.7A ,be Low batt will slow charge (6) DISCONNECT_IO : Current sense differential voltage threshold for driving disconnect FET High when I 0.12AP.5011BY

14、 Louis Cao 07/17/2012FIRST RESET SIGNALHomeSMSMS SC CU25VCC1_POR#_3The VCC_POR# just can low at reset point.So it can not lack any part. +V3ALWAYS+V3ALWAYSSTBY_SWIN#_3PWR_SWIN#_3+V3ALWAYSEVCC1_POR#_3P.31R241R242,R243R719DOCKINGCNTRCN516When docking is not present, the EBOXL#, EBOXS# should be go Hi,

15、 or booting will be delayed about 15 sec.So it can not lack any part.EBOXL#_3EBOXS#_3R508,R519R518,U502P.35ACPRES_3DCPRES_3P.41RSMRST#_3When the other 5 parts are OK, the RSMRST# will go Hi. In the other word, this pin go Low only when the system reset.If BIOS data is error,RSMRST# wont go HI.BIOSin

16、tel.CN9P.20X3+V_RTCP.19CrystalC296 C297When SMC get +V_RTC the crystal will work.32.768kHz(XOSEL)R32412BY Louis Cao 07/17/2012ACPI STATES SUPPORTEDHomeSystem States :CPU States :(1) G0/S0 : Full On (2) G1/S1 : Power On Suspend(POS).System Context Preserved. (3) G1/S3 : Suspend to RAM(STR). Power and

17、 context lost to chipset.(4) G1/S4 : Suspend to Disk(STD). All power lost(except wakeup on ICH3-M). (5) G2/S5 : Hard off. Total reboot. (1) C0 : Full On (2) C1 : Auto Halt. (3) C2 : Quick Start(Lower power than Stop Grant).(4) C3 : Deep Sleep. Clock to CPU stopped. 13BY Louis Cao 07/17/2012ACPI STAT

18、ES SUPPORTEDHomeGlobal(G)stateSleep(S)stateCPU(state)Processor stateDescriptionGOS0COFull on Full onGOS0C1Auto-HaltAuto-HaltGOS0C2Quick startQuick startGOS0C3Deep sleepDeep sleepG1S1C3Deep sleepPower on suspendG1S3Power OffPower OffSuspend to RAMG1S4Power OffPower OffSuspend to DiskG2S5Power OffPowe

19、r OffHard offG3NAPower OffPower OffMechanical off14BY Louis Cao 07/17/2012RSMRST#_3 to ICH3HomeU518ICH3intel+V3A_ICH+V_RTCRTCBATX50032.768KHzL518+V3ALWAYSBeforehand1RSMRST#_33SLP_S1#_3RSLP_S3#_3RSLP_S5#_3RR115R664R662PCI_RESET#_3R6462SLP_S1#_3R : LOWSLP_S3#_3R : LOWSLP_S5#_3R : LOWPCI_RESET#_3 : LOW

20、4SLP_S1#_3R : HIGHSLP_S3#_3R : HIGHSLP_S5#_3R : HIGHPCI_RESET#_3 : LOW15BY Louis Cao 07/17/2012HomeENABLE DC/DC CIRCUITRYSLP_S1#_3R : Assertion( transition from logic “1” to logic “0”) Active Low. SLP_S5#_3R : The signal is used to shut power off to all non-critical systems when in S4(Suspend to Dis

21、k)state. When signal is High : (1) +V5 from P/B (2) +V3 from +V3ALWAYS across U511,R576,and Q511P.4, P.13,P.24P.41, P.47Sequence : +V5 +V3 16BY Louis Cao 07/17/2012HomeENABLE DC/DC CIRCUITRYSLP_S3#_3R : The signal is used to shut power off to all non-critical systems when in S3(Suspend to RAM)state.

22、 When signal is High : (1) +VTT (U505-MAX1715) P.47 and P.48-+VCC (2) VTT_S3# (R599) 1. +V3S from +3ALWAYS across U511,R553,and Q511. 2. +V1.8S from +V1.8ALWAYS across U511,R666,and Q513 3. +V4.8S_A from +V5 across U33. 4. +V5S from +V5 across U511,R574,and Q512 When signal is Low : (1) +VTT,+3VS,+V

23、1.8S,+v4.8S_A,and +V5S will power off. (2) AUDIO will no sound (SHUTDOWN ACTIVE)Q517,R771,and U31P.47P.47P.24P.47P.26Sequence : +V5S +V3S +V1.8S 17BY Louis Cao 07/17/2012HomeCPU MASTER POWER+VTT : NO change POWER+VCC : Variable POWER MAX 1715 The detail circuit require to see page 47 .(1)When +VTT a

24、nd +V1.8ALWAYS is ok, the PGOOD(pin7) of MAX1715 will High(2)PGOOD VTT_PWRGD_3 GSV (U504-MAX1718) VTT_PWRGD#_3 GSV (U504-MAX1718) VTT_PWRGD CPU (U525) (3)U504 send to VGATE_U (Have a pull up resistor 8.2K ohm)(4)V_GATE_U VGATE_3 ICH3(Geyserville controller) PM_GMUXSEL = “1” for High-voltage , “0” fo

25、r Low-voltage P.47 , P.48P.49P.18 , P.4918BY Louis Cao 07/17/2012HomePower Good signalPWR_GOOD_3Required : (1) Power ok +V3S , +V2.5S , +V1.8S , +V5S , +V3 +V1.5S , +V5ALWAYS , 1.3VREF 2VREF , +V3ALWAYS , V3_ICHLAN +V1.8_ICHLAN (2) Control signal VGATE_U VGATE_3 SLP_S3#_3RP.49When ALL POWER are READ

26、Y ,the PWR_GOOD_3 will go Hi to SMC.19BY Louis Cao 07/17/2012HomeCLOCK SUMMARY(1) 32.768KHz :X3 to SMC (SIO) , Required +V_RTC X500 to ICH3 (chipset) , Required +V_RTC(2) 49.152MHz :X502 to ESS1988 (audio controller) Required +V3S , SLP_S1#_3R to HI(3) 27MHz :X2 to ATI_P6 (video controller) Required

27、 +V3S , SLP_S1#_3R to HI(4) 25MHz :X501 to ITL (Lan controller) Required +V3S(5) 14.318MHz :X1 to ICS950805 (clock Generator) Required +V3_LANP.19P.18P.24P.13P.4P.4620BY Louis Cao 07/17/2012HomeCLOCK SUMMARYClock Generator(ICS950805-U7)Functionality : SEL0 , SEL1 , SEL2 : ALL to HI (R586,R587,R593-+

28、V3S) (1) CPU0CPU2 & CPU0#CPU2# : 133.33MHz(2) Almator-M/GMCH3 transfer 66MHz to 66INPUT(3) 66BUF066BUF2 : 66MHz(4) PCI1PCI6 & PCIF0PCIF2 : 33MHz(5) REF : 14.318MHz(6) USB : 48MHz(7) DOT : 48MHzElementary required : (1) Power : +V3S(2) Crystal : 14.318MHz(3) Control : SLP_S1#_3R is HI , PCISTOP#_3 is HI , CPUSTOP#_3 is HI P.421