频率补偿研究心得

1、Research on Multistage Amplifier Frequency Compensation 概括放大器为模拟设计中的核心功能模块。 CMOS 技术下低电压使得多级成为必然, 频率补 偿用于保证良好的频率特性。 目前所提出的几乎所有的频率补偿技术都是基于 NMC 和 RNMC , 并且围绕着这两种补偿方式在高稳定性, 快速暂态响应, 低功耗, 芯片面积等方面进行优化。 经过对频率补偿的研究,建立了理论框架,熟悉了各种补偿电路 , 完成了初期的理论积 累, 为后期进行深入研究奠定了良好基础。 在这篇文章里, 我将着重谈谈我对各种补偿电路 的研究体会和理解认识,简要推导电路极零点

2、表达式并大概介绍一下其频率特性。电路分析一、 (NMC Nest Miller Compensation Fig 1.Nest Miller CompensationIn the three stage NMC topology, there are two Miller capacitors Cm1and Cm2connected from the output to the output of each stage, respectively. There is a large capacitive load which makes the pole at the output very

3、close to the dominant pole at the output of the first stage. Both poles are located at low frequency, posing a great threat to the stability of the amplifier. Pole-splitting using compensation capacitors and pole-zero cancellation using feed-forward paths seem to be the obvious solutions to remove t

4、he effect of the pole. The use of a feed-forward path to cancel this pole is risky because an imperfect pole-zero cancellation at low frequencies creates a pole-zero doublets and deteriorates the settling time of the amplifier. This leaves us with the only choice of pole splitting using a Miller com

5、pensation capacitor. That is why almost all the frequency compensation scheme based on NMC add a capacitor between the output of the first and third stage。The Miller capacitors Cm1and Cm2form two negative feedback loops to stabilize the amplifier but seriously reduce the high frequency gain. As a re

6、sult, extra power is needed to compensate this gain reduction. Moreover, the Miller capacitor Cm2that shorts the last stage gives the additional disadvantages that the phase shift reaches 180°as frequency increases, leading to a positive feedback loop involving Cm1, gm2, and Cm2, which is a ser

7、ious source of instability. Therefore, the trans-conductance gm3must be large enough to counter this shorting effect, thus, it is not suited for low-power applications.To analyze the stability of the NMC amplifier, the small signal transfer function of the NMC amplifier shown in Fig.1 will be invest

8、igated.首先分析一下我对极点的直观认识。 极点反映在波特图上, 即为增益曲线的拐点。 从能量的角度看, 电容能量耗散随着频率升高而加剧。 从电压角度看, 电容阻抗随频率升高而降 低导致每一级输出阻抗降低。从电流角度看,频率升高,使电容吸取信号流的能力增强,而 电阻呈现出相对高阻抗。 极点的物理意义可以理解为电阻电容分流的临界点。 在低频处, 高 频极点电容分流低于电阻,故电容可看作开路,信号流近似全部流经电阻,形成直流增益。 在高频处,低频极点电容分流高于电阻,故电容可看作短路,信号流近似全部流经电容,进 行能量耗散。对图 Fig.1所示 NMC 的极点进行直观分析。 首先每一级的输出寄

9、生电容远小于所连接的 补偿电容,故可看作开路。在主极点 P0附近,高频点处的电容 Cm2, CL看作开路,信号流过对 地电阻形成高电压增益, Vout =gm2R2gm3RLVA。 A 点相对 OUT 点可近似看作零电位, OUT 点通过 Cm1向 A 注入信号流 Vout sCm1,该值应等于 A 点通过到地电阻的分流。因此有 VAgm2R2gm3RLsCm1=VAR1 (1 即为 P0=1gm2R2gm3RLCm1R1 (2 在此基础上,当频率继续升高, Cm1看作短路,两端近似等电位。当频率升高至第一次 极点 P1时, B 点达到电阻电容分流临界点。 我们利用 gm2激发的信号流全部流经

10、 Cm2的近似关 系得到次极点 gm2VA=sCm2VA(3 即为 P1=gm2Cm2 (4 再分析第二次极点 P2,电容 Cm2两端电位近似相等。由 gm3激发的信号全部流经负载电 容 CL。对点 OUT 点有 gm3VB=VBsCL(5 即为 P2=gm3CL (6 以上直观的分析方法避免了繁琐的计算, 可以很快地得到极点表达式, 不过有一定误差。 接下来,我将提出更精确的分析方法。该方法可以便利地计算出次极点及零点表达式。 上面的论述中已经分析过多级频率补偿普遍采用弥勒电容分离 P0和 P2。 因此几乎在所有 的补偿电路中主极点都具有相同的表达方式,如式 (2。因此我们需要分析的是三级放

11、大器 中两个次极点。在次级点频率范围内, Cm1两端近似等电位。电容分流占主导,电阻近似看 作开路。只剩下跨导和补偿电容,利用 A 与 OUT 近似等电位的关系可以列出下式gm2VA+(gm2VAsCm2+VA (gm3 =VAsCL(7 With the assumption of gm3 gm2, equation (7 can be simplified as1+sCm2 gm2 +s2CLCm2gm2gm3=0(8接下来再分析电路的零点。 零点的频率范围远高于主极点, 和上面原理相似。 我们将输 出电位置零,则有gm1Vin*1+gm2 sCm1 (1+gm3sCm2+=0(9即为 s

12、2Cm1Cm2+sCm2gm2 gm2gm3=0(10 From equation (10, since there are one RHP zero and one LHP zero, and the RHP zero locates at a lower frequency. It is known that the RHP zero degrades the stability significantly, although it was not taken into account in the early literature, for low-voltage low-power C

13、MOS designs the removal of the right-half-plane (RHP zero is mandatory. There are many methods to eliminate the RHP zero and improve the bandwidth. The methods involve using voltage buffer and current buffer, a nulling resistor, and MZC technique.From another aspect, to ensure stability, the last st

14、age trans-conductance gm3required in a three stage NMC amplifier is given bygm3 4(2GBWCL(11Apparently, in a NMC amplifier, the required trans-conductance for the last stage alone is four times the trans-conductance for a single-stage amplifier. It is thus not suited for low-power applications. Obvio

15、usly, this power consuming effect is mainly caused by the inner Miller capacitor Cm2. The first Miller capacitor Cm1causes the slope to be -20dB per decade in frequency, as in any amplifier. Hence, it is the second Miller capacitor Cm2which causes an unnecessary reduction in high-frequency gain such

16、 that a large trans-conductance gm3is needed for the last stage.Based on these considerations, it becomes clear that taking away the inner Miller capacitor Cm2could be a possible way to achieving better performance. However in this case the first non-dominant pole would be determined by parasitic ca

17、pacitances, resulting in layout-sensitive circuits. Moreover, a safe gain margin would not be ensured due to the effects of the zeros caused by the parasitic capacitances. Besides, since the second stage dc gain AV2appears in the expression of the first non-dominant pole as a multiplier to other par

18、ameters, the sensitivity must be high.For sake of comparison, the case that the inner Miller capacitor is excluded from the three-stage NMC topology is discussed and presented in the next section.二、 UMC (Unique Miller Compensation Fig 2.Single Miller CompensationThe case that the inner Miller capaci

19、tor is excluded from the three-stage NMC topology is referred to as Unique Miller Compensation (UMC, which is shown in Fig.2. The function of the gmfis to implement a push-pull output stage to improve the slewing performance.First the pole will be analyzed, as there is no Miller capacitor at the out

20、put of the second stage, signal will flow directly to ground through output conductance. We can obtaingm2gm3sC2+go2 gmf=sCL(12 极点表达式为s2CLC2+s(CLgo2+gmfC2 +gmfgo2+gm2gm3=0(13 With the assumption of CLgo2 gmfC2, gm2gm3 gmfgo2, we haves2CLC2+sCLgo2+gm2gm3=0(14First non-dominant pole P1=gm3gm2 CLgo2 =AV

21、2gm3CL(15Second non-dominant pole P2=go2 C2 =1Ro2C2(16Although C2is a lumped parasitic capacitance, the second non-dominant pole P2cannotbe kept high since the second-stage output resistance Ro2 is large with regard to the other small equivalent resistance 1/gm. Consequently, this results in a compl

22、ex-pole arrangement for the non-dominant poles.Then analysis the zero point: 1+1sCm(gmf+gm2gm3sC2+go2=0 (17 Calculate ass2CmC2+s(Cmgo2 gmfC2 gmfgo2 gm2gm3=0(18In the unity-feedback configuration, to ensure a third-order Butterworth frequency response with the damping ratio =12Q=0.707, the stability

23、conditions are given byGBW =12P1=12AV2gm3CL=14P2=141Ro2C2(19Clearly, the stability conditions given by (19 are hard to maintain, since both AV2 and Ro2 cannot be accurately specified. They are greatly dependent on the operating points of the relevant transistors. Moreover, the lumped parasitic capac

24、itance C2, which is also imprecise, can inevitably lead to vulnerable layout-dependent circuits. In conclusion, with the three imprecise values: AV2, Ro2, and C2, the stability condition (19 cannot be reliably ensured in practical implementations. Even if the feed-forward stage gmf is taken into acc

25、ount, the effects of the imprecise parameters are still in existence. As such the problem remains unsolved. Therefore, other topologies have to be devised. 三、DFCFC1 (Damping Factor Control Frequency Compensation Fig 4.Damping Factor Control Frequency Compensation(gmVin+i RL=vin i1sCm(20With the assu

26、mption of gmRL 1, we can obtaini =1+gmRLRL+mVin gmRLRL+mVin(21若有 RL 1sCm , 则 i =gmRLsCmVin; 若有 RL 1sCm , 则 i =gmVin, 相当于大小为 1gm 的电阻。直观上理解为当频率低于极点时,信号流大部分由 RL到地,形成较大的电压 增益,从而输入点相对输出点可看作零电位,从输出通过 Cm向输入注入信号流 sCmVout。当 频率高于极点时, Cm阻抗变得足够小,以至于 gm激发的信号流近似全部流过 Cm, RL相当于开路。有个疑问,在此 DFC 中需要屏蔽负载,使信号只流过 gm和 Cm。方

27、式有两种,一种是提 升负载,形成低频极点,如此在高频下低频极点电容分流占主导,电阻看作开路。但另一种 理解方法为降低负载,通过内部负反馈环路稳定 DFC 内部直流点,使输出直流恒定,可看 作交流地,从而负载被屏蔽,不再有信号通过。或者理解为利用降低增益技术使 DFC block 输出近似为交流地,但为保证 gm的控制作用,其增益不能低于 1,即内部环路增益不能高 于 DFC 本身增益。这两者间有何关联之处? iDFCFC1基于 SMC 在第二级输出增加了 DFC 模块。有效地改善了 UMC 稳定性控制不足 的问题。该模块的频率特性我们已经在前面讨论过,等效为跨导为 gm4的压流源或阻值为 1g

28、m4 的特殊阻抗。 特殊性在于该阻抗不影响原电路低频直流增益, 而是通过分流作用有效 控制电路稳定性。故在分析次级点时可将 UMC 中 go2替换为 gm4,由于 gm4 go2,故有效 增强了对阻尼系数的控制。改写极点表达式 (13式和零点表达式 (18式如下s2CLCp2+s(CLgm4+gmfCp2 +gmfgm4+gm2gmL=0 (22 s2Cm1Cp2+s(Cm1gm4 gmfCp2 gmfgm4 gm2gmL=0 (23With the assumption of CL Cp2,分别化简得 极点表达式 1+s CLgm4gmfgm4+gm2gmL+s2CLCp2gmfgm4+gm

29、2gmL(24 零点表达式1+sgmfCp2Cm1gm4gmfgm4+gm2gmL s2Cm1Cp2gmfgm4+gm2gmL(25由假设条件 Cm1 Cp2,式 (25的 s1项为负,可能引入低频正零点,于稳定性不利。该低频正零点为 Z = gmfgm4+gm2gmLgmfCp2Cm1gm4 gmLCm1(1+gm2gm4=gmLgm1gm1Cm1(1+gm2gm4(26 即为Z =gmLgm1(1+gm2gm4(27为保证不受 RHP ZERO影响,需要 Z 提升至 10GBW 处,由式 (27,将增大功耗。若忽略零点影响,由三级巴特沃斯频率响应得gm4=(Cp2CLgm3(28nulln

30、ullnull路增益降低，导致等效电阻升高，性能恶化。另一方面即为反馈回路内部稳定性的问题，反 馈越深，补偿难度越大。还有就是反馈回路可能引入低频极零点，这将有可能影响外部系统 稳定性。 基于 current buffer 的补偿方式还有若干变形，如 DLPC 10，原理很简单，为了提高带 宽，去掉内层弥勒电容并增加阻尼系数控制。 频率补偿用途很广， 不仅用于放大器设计， 还用于反馈回路， LDO 的回路补偿， 如 current buffer 中的反馈回路补偿等。 Conclusion 此次研究频率补偿，一方面是作为 Linear Voltage Regulator 的延伸，另一方面也是为今

31、 后研究更复杂的回路频率补偿奠定基础。 反馈回路一方面涉及反馈理论， 另一方面涉及频率 特性，如稳定性和暂态特性。回路在电路系统中无处不在，小到放大器，大到锁相环，从内 部模块的局部回路，到系统级的大回路，环环相扣，因此对于反馈回路频率特性的分析极其 重要。从小信号和大信号，静态和动态，稳定和震荡（VCO） ，不同的角度进行分析。另外 基于反馈回路的噪声抑制问题也很重要。这些在今后的学习中都要仔细分析，加以深化。 Reference 1 Song Guo, Hui Lee, ”Single-Capacitor Active-Feedback Compensation for Small Cap

32、acitive Load Three-Stage Amplifiers,” IEEE Trans. Circuits and Systems, vol.56, pp758-762, 2009. 2 A. Pugliese, G. Cappuccino, G. Coorullo, “Nested Miller compensation capacitor sizing rules for fast-settling amplifier design,” IEEE Electronic Letters, vol.41, pp.573-575, 2005. 3 J. Ramos, P. Xiaohong, “Three Stage Amplifier Frequency Compensation,” IEEE J. Solid-State Circuits, pp.365-368, 2003. 4 Ka Nang Leung, Mok, P. K. T, “Three stage large capacitive load amplifier with damping factor control frequency compensation,” I