一个可用于PET和SPECT镜像的高速率的USB数据采集系统的应用中英文翻译

1、我们在以灵活高效的usb数据采集系统的研制伽马射线成像探测器方面取得了实质性的进展。该硬件由安装在usb接口的载波板上的16通道数据采集模块组成。一，二，和四模块单元是经过该良的。 usb数据采集率增加至超过30 mb/秒并且一个16通道结构可以达到触发率超过700千赫。该设备还装备了几个高分辨率单伽马射线探测器和两个高效率pet探测器。该探测器采用hamamatsu h8500，h9500 ，burle 85002-800 pspmts等多种配置。同步额外采集单元扩展了系统通道。一个java客户机-服务器系统被改良后通过超过千兆的以太网连接到采集计算机上。一个kmax工具是用来在采集数据时处

2、理和显示图像的。 c和java的功能发展可以帮助开发和诊断。i.简介一种新型高速的以usb为基础的数据采集系统先前被加工后装备在由杰弗逊实验室检测和影像小组1设计的伽玛射线成像探测器上。它成功地展示了多种探测器和结构。即便在保持很高的触发利率的前提下可扩展性从16到128通道都可以成功完成。我们还成功地装备了几个配有hamamatsu h8500和h9500位置灵敏光电倍增激光器（pspmts）的低速率高分辨率单伽马射线的探测器。我们还装备了一台配有h8500 pspmts的pem/pet探测器和一台配有burle 85002-800 pspmts的心脏pet探测器。我们在数据采集和处理架构放

3、面取得了重大的实质性进展。为了能高速率应用，我们开发了一个java客户机-服务器系统。对于低速率时，为了能实时影像处理，我们开发了kmax jave扩展部分来与数据采集单位直接通信。c和java的功效发展有助于数据采集系统硬件的开发和诊断。我们成功地装备了不同的pspmts，不同闪烁器，不同的pspmt电阻耦合器，这些都是使用相同的数据采集结构。原始图像由所有的装配有这样系统的探测器所展示。该数据采集系统可由两个同步64通道单元扩展为128通道，并且在软件上融合了实时追踪系统。这种技术将使我们能够将其扩大到任意数目单位。它还将使我们能够在实时同步数据采集系统中囊括不包含ad转换的装置，比如时间

4、数字转换器（tdcs ） ，数字输入/输出接口等等。他们各自的实时追踪实例将合并成一个单一的混合实例结构。ii.硬件每个数据采集单元的16通道数据采集模块通过高速usb接口安装在一个载板上。每个通道是一个独立的采集单元，该单元由传统的模拟脉冲加工，fpga模拟控制，和fpga数字处理组成。经过数据采集与处理，通道数据组合成实例数据块以便载板将其读取。每个实例将被标注上一个10纳秒的时间标签。该时间标签是用来通过几个数据采集单位重组实例分布的。它也可以被用来做动态研究。a. 载板该64通道载板可以承受多达四组16通道的模块。它从模块中读取实例，并组合他们以便由usb主机电脑读取。16和32通道单

5、位有一个和两个模块，独立的，但在其他方面完全相同。这样的64通道单位的体系结构由图1所示。64，32和16通道单位的成品封装照片分别如图2-4所示。该载板将时间信号在数据采集模块和数据采集单位之间进行分配。它可以看作为时间的掌管者，也可以看作是服从者。作为掌管者，它提供了自己和外部单位的时钟和复位信号。作为一个服从者，它接收外部机构的时间信号和并将时间信号转播给其他的服从者。载板将提供公用设备，比如一个可编程脉冲发生器，触发计数器，速率计数器，用户可访问电可擦除只读存储器。它有两个8位供电的双向ttl输入/输出端口，这两端口个可与外部设备通信，如电平转换器，模数转换器，数模转换器，等等。其中一

6、个端口通常被设置为输入一个外部ttl触发和输出一个积分门监控。该系统通常被设置为执行全部触发的同步采集工作。采集器是被一个载板上的信号触发的。触发源可以是任何一个输入通道，一个外部的ttl信号，或一个内部脉冲发生器。该触发由一个不可重复触发的脉冲承担，然后同时转发给所有模块。 当所有模块报告接收到该触发后，载板指示这些模块接收实例。否则，实例将被清除。由于使用了手动触发，灵活实例缓冲，和触发脉冲加工，我们可以在任何触发率和模式下完美地组合实例。b. 数据采集模块图5描述了16通道数据采集模块其中的一个频道。模拟部分包括一个具有领先地位的附带12位入端数模转换器的鉴识器，一条8阶50纳秒模拟延迟

7、线路，一个附带12位输入偏差数模转换器的电压门控积分器，以及一个12位的2.5兆赫可触发特别模数转换器。所有模拟功能是被fpga通过单一通道或在通道之间控制的，fpga允许可编程模拟控制结构。fpga的数字化处理过程可以对单一通道或实例主要部分本身执行。信道处理可以包括鉴识窗口控制，分析结论读出，偏差和补偿校正，脉宽测量，柱状图等。实例处理可以包括实例组合，计算，缓冲，总和管理，鉴识窗口，禁止，等等。实用功能可以包括可编程触发模式，动态偏移校正等。实例可以被一个数字计算机上的高分辨率的实时记录设备纪录。目前实例组合通常采用10纳秒实时纪录，而5纳秒也已经成功地通过试验，不仅如此，更高分辨率的实

8、时纪录也是完全可能的。在目前的配置中，数字处理系统包括零点抑制，可编程触发源，和40位10纳秒触发实时纪录器。所有的通道都是同时触发和获取数据的。原始和共同的触发器以及触发利率都要依靠载板。如果不需要积分的话，那么积分器就失效了，而且模数转换器会在编程选通脉冲宽度后取样。该选通脉冲因此可以作为一个可编程的取样延迟。由于硬件通常是优化组合的，那么即使是一个小小的硬件改动（每个通道的任何一个电阻）都需要优化取样。c.可测量性该数据采集系统具有高度的可扩展性。一个需要很少通道的系统可以通过一个数据采集单元和一个读计算机来达到一个很高的触发率。对于许多的高触发率通道来说，几个单元可以通过一个时间分配系

9、统而同时工作并且每个单元会被分派到它自己的采集计算机。通过一些单元或计算机分配的实例会利用软件通过实时纪录系统重新组合。d触发率对于磁盘的持续usb数据传输速率可以增至每秒30兆字节。 这样可以使16通道的持续触发率增加至超过700千赫，32个频道增加至超过350千赫，64频道增加至超过175千赫。触发率超过125千赫的情况下已达到128通道pet探测器。由于频率主要是受usb带宽的限制， 那么零点抑制将允许触发率上升到通常所允许的最高为1兆赫的转化率。最高频率是由积分，取样和存储所需时间总和所决定的。采用流水线技术，更高频率是有可能实现的，但目前此技术尚未落实。iii软件我们开发了几个采集与

10、处理的结构。在所有情况下，高功效的核心采集功能在c语言环境下完成的。而应用中的具体任务是通过java语言编写的。我们开发了三个不同的软件平台。kmax是用于探测器的开发和低频率实时成像。一个java客户机/服务器系统是为分布式高速率多单元系统而开发。还有一个综合了c和java功能的平台是为数据采集系统的发展和诊断而设计的。a.kmaxjava到kmax的延展部分的开发是为了能与数据采集系统硬件中的kmax衔接。kmax采集原始数据， 计算质心，校正，并实时显示原始的和校正后的图像。我们实现了64通道50千赫触发率。kmax是一个很方便的用于开发和描述适中触发率的探测器的工具。这种结构如图六所示

11、。b.java一个java客户机/服务器系统是为需求高频率多渠道的探测器而开发的。每个数据采集单元都连接到一个数据采集电脑。该数据采集电脑（服务器）通过千兆以太网连接到"实例源" （客户）计算机，这些计算机都从服务器上融合了单独的实时记录实例。客户端控制所有服务器功能，如硬件配置和采集参数。图12描述了这样一个pet应用结构。该数据采集服务器可以在采集期间或者或者采集后进行图像校正。而处理过的数据发送给客户端，原始数据都存储在服务器上，如果需要的话也可以发送到客户端。合并后的客户数据发送给计算机进行图像重建。我们希望数据采集，处理和在各个系统之间传输可以同时发生，并且尽可能

12、最小地影响采集速率。客户机-服务器软件可以存储在单一的计算机上。这样可以在触发率低时由一台电脑来管理多个附加的数据采集单元。c.c和java部分一个由c和java合成部分是为数据采集系统的硬件而开发的。这些执行了简单的采集，硬件和驱动功能测量，分析实例缓冲器，并检测了所有的硬件功能。 这些都用于硬件诊断和原始数据采集。附录bimplementation of a high-rate usb dataacquisition system for pet and spect imagingabstractwe made substantial progress with a flexible hi

13、gh-rate usb data acquisition system developed for gamma-ray imaging detectors. hardware consists of 16-channel data acquisition modules installed on usb carrier boards. one， two， and four-module units were developed. usb data rate was increased to over 30 mb/s and a 16-channel configuration achieved

14、 a trigger rate of over 700 khz. several high-resolution single-gamma detectors and two high-rate pet detectors were instrumented. the detectors use various configurations of hamamatsu h8500， h9500， and burle 85002-800 pspmts. system channels were expanded by synchronizing additional acquisition uni

15、ts. a java client-server system was developed to link acquisition computers over gigabit ethernet. a kmax tool was developed to process and display images during acquisition. c and java utilities were developed to assist development and diagnostics.i. introductiona new high-speed usb-based data acqu

16、isition system was previously developed to instrument the gamma-ray imaging detectors designed by the jefferson lab detector and imaging group 1. it was successfully demonstrated on a variety of detectors and configurations. scalability from 16 to 128 channels was achieved while preserving high trig

17、ger rates. we successfully instrumented several low-rate high-resolution single-gamma detectors that use hamamatsu h8500 and h9500 position-sensitive photomultipliers (pspmts). we also instrumented a high-rate pem/pet detector that uses h8500 pspmts and a cardiac pet detector with burle 85002-800 ps

18、pmts.we made substantial progress with the daq acquisition and processing architecture. for high-rate applications， we developed a java client-server system. for low-rate， real-time imaging， we developed kmax java extensions to communicate directly with daq units. c and java utilities were developed

19、 to assist daq hardware development and diagnostics.we successfully instrumented different pspmts， different scintillators， and different pspmt resistive coupling， with the same daq configuration. raw images from all detectors instrumented to date with this system are presented.the daq system was ex

20、panded to 128 channels using two synchronized 64-channel units and merged time-stamped events in software. this technique will allow us to expand to an arbitrary number of units. it will also allow us to include non-adc devices such as time-to-digital converters (tdcs)， digital 1/0， etc. in the time

21、-synchronized daq system. their respective time-stamped events would be merged into a single hybrid event structure.ii. hardwareeach daq unit consists of 16-channel daq modules installed on a carrier board with a high-speed usb interface. each channel is an independent acquisition unit consisting of

22、 traditional analog pulse processing， fpga analog control， and fpga digital processing. after sampling and processing， channel data are assembled into event blocks for readout by the carrier board. each event is tagged with a 10ns time stamp. the time stamp is used to reassemble events distributed a

23、cross several daq units. it can also be used for dynamic studies.a. carrier boardthe 64-channel carrier board accepts up to four 16-channel modules. it reads events from the modules and assembles them for readout by the usb host computer. the 16 and 32 channel units have one and two modules， respect

24、ively but are otherwise identical. the architecture of the 64-channel unit is show in fig. 1. photographs of the production 64， 32， and 16 channel units with enclosures are shown in fig. 2-4 respectively.the carrier provides timing distribution to the daq modules and between daq units. it can act as

25、 a timing master or slave. as a master， it provides clock and reset to itself and to external units. as a slave， it receives external timing and retransmits the timing to other slaves.the carrier provides utilities such as a programmable pulse generator， trigger counters， rate counters， and user-acc

26、essible eeprom. it has two 8-bit powered ttl i/0 ports for bidirectional communication with external devices such as level translators， adcs， dacs， etc. one port is currently configured to input an external ttl trigger and output an integrator gate monitor.the system is currently configured to perfo

27、rm simultaneous acquisition on a global trigger. acquisition is triggered by a signal from the carrier board. the trigger source can be any input channel， an external ttl signal， or the internal pulse generator. the trigger is processed by a non-retriggerable pulse stretcher then transmitted to all

28、modules simultaneously. when all modules report that the trigger was accepted， the carrier instructs the modules to accept the event. otherwise， the event is cleared. by using trigger handshaking， flexible event buffering， and trigger pulse processing， events can be assembled flawlessly for any trig

29、ger rate or pattern.b. daq moduleone channel of the 16-channel daq module is described in fig. 5. the analog portion consists of a leading-edge discriminator with 12-bit threshold dac， an 8-stage 50ns analog delay line， a gated voltage integrator with 12-bit input offset dac， and a 12-bit 2.5 mhz tr

30、iggerable sar adc. all analog functions are controlled through the fpga which permits programmable analog control configurations within a channel and between channels.fpga digital processing can be performed on a channel or event basis. channel processing may include charge window discrimination， sp

31、arsified readout， offset and gain correction， pulse width measurement， histogramming， etc. event processing may include event assembly， counting， buffering， charge sum， window discrimination， veto， etc. utility functions may include programmable trigger pattern， dynamic offset correction， etc.events

32、 can be tagged with a high-resolution time stamp derived from a digital counter. while a 10ns time stamp is currently used for event assembly， 5ns has been successfully tested and higher resolutions are possible. in the present configuration， digital processing includes zero-suppression， programmabl

33、e trigger source， and a 40-bit 10ns trigger time stamp. all channels are triggered and acquired simultaneously. raw and accepted triggers and trigger rates are counted on the carrier board. if integration is not required， the integrator can be disabled and the adc will sample after the programmed ga

34、te width. the gate width would therefore serve as a programmable sampling delay. since the hardware is normally optimized for integration， a small hardware change (one resistor per channel) is required to optimized for sampling.c. scalabilitythe dac system is highly scalable. a system requiring few

35、channels can achieve a high trigger rate with one daq unit and one readout computer. for many high-rate channels several units can be synchronized through a common timing distribution system and each unit assigned its own acquisition computer. events distributed across several units/computers are re

36、assembled in software using event time stamps.d. trigger ratessustained usb data rate to disk was increased to 30 mb/s. this increased sustained trigger rates to over 700 khz for 16 channels， over 350 khz for 32 channels， and over 175 khz for 64 channels. trigger rates exceeding 125 khz have been ac

37、hieved for a 128-channel pet detector.since the rate is primarily limited by usb bandwidth， zero-suppression would permit trigger rates up to the currently allowable maximum conversion rate of 1 mhz. the maximum rate is determined by the sum of time required to perform integration， sampling， and sto

38、rage. higher rates are possible using pipelining techniques not currently implemented.iii. softwareseveral acquisition and processing configurations were developed. in all cases， high-performance core acquisition functions are performed in c. application specific tasks are performed in java. three d

39、ifferent software platforms were developed. kmax is used for detector development and low-rate real-time imaging. a java client/server system was developed for distributed high-rate multi-unit systems. a collection of c and java utilities were developed for daq development and diagnostics.a. kmaxjav

40、a extensions to kmax 2 were developed to interface kmax to the daq hardware. kmax acquires raw data， calculates centroids， applies corrections， and displays raw and corrected images in real time. we achieved trigger rates up to 50 khz for 64 channels. kmax is a convenient tool for development and characterization of detectors at a moderate trigger rate. fig. 6 diagrams this architecture.b. javaa java client/server system wa