[物理][第6章] 组合电路构件块ppt课件

1、组组 合合 电电 路路 构构 件件 块块延延 边边 大大 学学 工工 学学 院院电电 子子 信信 息息 通通 信信 学学 科科许许 一一 男男选选 择择 器器Multiplexers(mux)22 选选 1 选选 择择 器器(mux)3 s: 选择选择信信号号(select signal) W0, W1: 输输入信入信号号 (input signals) f: 输输出信出信号号 (output signal) sf0w01w12by1 mux 真值真值表表:2 选选 1 选选 择择 器器 图图 形形 符符 号号4w0w1f01ssf0w01w12by1 mux 真值真值表表:2by1 mux

2、图图形符形符号号5sf0w01w12by1 mux 真值真值表表:w0w1sf2 选选 1 选选 择择 器器(mux)电电 路路6w0w1sf2选选1选择选择器的器的Verilog HDL编编程程(1)module mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodulesf0w01w17module mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodule2选选1选择选择器的

3、器的Verilog HDL编编程程(2)module mux2to1 (w0, w1, s, f); input w0, w1, s; output reg f; always (w0, w1, s) f = s ? w1 : w0;endmodule82选选1选择选择器的器的Verilog HDL编编程程(3)module mux2to1 (w0, w1, s, f); input w0, w1, s; output reg f; always (w0, w1, s) f = s ? w1 : w0;endmodulemodule mux2to1 (w0, w1, s, f); input

4、w0, w1, s; output reg f; always (w0, w1, s) if (s=0) f=w0; else f=w1;endmodulemodule mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodule测试测试程序程序Test Bench) ?要求要求1： 时时延延单单位位为为1ns, 时时延精度延精度为为100ps 2： 单单位位时时延延delay) = 50ns 3: 经过经过1个单个单位位时时延后延后选择选择w1, 4: 经过经过2个单个单位位时时延后延后

5、选择选择w0, 5: 经过经过4个单个单位位时时延后延后选择选择w1, 6: 经过经过2个单个单位位时时延后延后选择选择w0, 7: 经过经过3个单个单位位时时延后延后选择选择w1,timescale 1ns/1nsmodule tb_mux2to1; reg 1:0 w; reg s; wire f; parameter DELAY=10;mux2to1 M2to1 (.w(w), .s(s), .f(f); /always #(DELAY/2) clk=clk; initial begin w=2b10; s=1b0; #DELAY s=1; #(DELAY*2) s=0; #(DELAY

6、*4) s=1; #(DELAY*2) s=0; #(DELAY*3) s=1; #(DELAY*100) $finish; endendmodule 测试测试程序程序Test Bench) 新建文件新建文件夹夹D:mux2to1) ModelSim 环环境境新建工程新建工程New-Project) 工程工程称号称号mux2to1) 建立新文件建立新文件mux2to1)建立新文件建立新文件tb_mux2to1)终终了了 编辑编辑程序程序 编编程程 主程序主程序编编程程测试测试程序程序 编编程程终终了了 Compile仿仿真真Simulate) 选择测试选择测试程序程序添加波形添加波形图图 运转

7、运转程序程序 否否 仿仿真结真结果果 4 选选 1 选选 择择 器器(mux)29 s: 选择选择信信号号(select signal) W0, W1: 输输入信入信号号 (input signals) f: 输输出信出信号号 (output signal) s1s0f00w001w110w011w34by1 mux 真值真值表表:4 选选 1 选选 择择 器器 图图 形形 符符 号号30w0w1f0001s14by1 mux 图图形符形符号号s1s0f00w001w110w211w34by1 mux 真值真值表表:1011w3w2s031s0f4 选选 1 选选 择择 器器 电电 路路s1s

8、0f00w001w110w211w34by1 mux 真值真值表表:s1w0w1w2w3301201101001ssssssss fwwww324选选1选择选择器的器的Verilog HDL编编程程(1)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodules1s0f00w001w110w211w34by1 mux 真值真值表表:33RTL (Register Transfer Level) 存存

9、放器放器传输级传输级module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodule344选选1选择选择器的器的Verilog HDL编编程程(2)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodulemodu

10、le mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else if (s=2b10) f = w2; else f = w3;endmodule35RTL (Register Transfer Level) 存存放器放器传输级传输级module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0

11、 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else if (s=2b10) f = w2; else f = w3;endmodule364选选1选择选择器的器的Verilog HDL编编程程(3)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else

12、 if (s=2b10) f = w2; else f = w3;endmodulemodule mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmodule374选选1选择选择器的器的Verilog HDL编编程程(4)module mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f

13、; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmodulemodule mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f; always (w, s) case (s) 0: f = w0; 1: f = w1; 2: f = w2; 3: f = w3;endmodule测试测试程序程序Test Bench) ?要求要求1： 时时延延单单位位为为1ns, 时时延精度延精度为为1ns 2： 单

14、单位位时时延延delay) = 50ns 3: 经过经过1个单个单位位时时延后延后选择选择w1, 4: 经过经过2个单个单位位时时延后延后选择选择w3, 5: 经过经过4个单个单位位时时延后延后选择选择w2, 6: 经过经过2个单个单位位时时延后延后选择选择w0, 7: 经过经过3个单个单位位时时延后延后选择选择w1,module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmoduletimescale 1ns

15、/1nsmodule tb_mux4to1; reg w0, w1, w2, w3; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w0(w0), .w1(w1), .w2(w2), .w3(w3), .s(s), .f(f); initial begin w0=1b0; w1=1b1; w2=1b0; w3=1b1; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*20) s=2b00; #(DELAY*3) s=2b01; #(DELAY*3

16、00) $finish; endendmodule测试测试程序程序Test Bench) (1)要求要求1： 时时延延单单位位为为1ns, 时时延精度延精度为为1ns 2： 单单位位时时延延delay) = 50ns 3: 经过经过1个单个单位位时时延后延后选择选择w1, 4: 经过经过2个单个单位位时时延后延后选择选择w3, 5: 经过经过4个单个单位位时时延后延后选择选择w2, 6: 经过经过2个单个单位位时时延后延后选择选择w0, 7: 经过经过3个单个单位位时时延后延后选择选择w1,s1s0f00w001w110w211w3ModelSim时时序仿序仿真结真结果果图图(1) Model

17、Sim时时序仿序仿真结真结果果图图(2) timescale 1ns/1nsmodule tb_mux4to1; reg 3:0 w; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w(w), .s(s), .f(f); initial begin w=4b0101; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*20) s=2b00; #(DELAY*3) s=2b01; #(DELAY*300) $finish; endendmodule测

18、试测试程序程序Test Bench) (2)要求要求1： 时时延延单单位位为为1ns, 时时延精度延精度为为1ns 2： 单单位位时时延延delay) = 50ns 3: 经过经过1个单个单位位时时延后延后选择选择w1, 4: 经过经过2个单个单位位时时延后延后选择选择w3, 5: 经过经过4个单个单位位时时延后延后选择选择w2, 6: 经过经过2个单个单位位时时延后延后选择选择w0, 7: 经过经过3个单个单位位时时延后延后选择选择w1,s1s0f00w001w110w211w3module mux4to1 (w, s, f); input 3:0 w; input 1:0 s; outpu

19、t reg f; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmoduleModelSim时时序仿序仿真结真结果果图图(2) 442选选1选择选择器器来实现来实现4选选1选择选择器器w0w101w2w301f01s0s1s1s0f00w001w110w211w34by1 mux 真值真值表表:M0M145Verilog HDL编编程程module mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f

20、=s?w1:w0;endmodulemodule mux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodule46Verilog HDL测试测试程序？程序？module mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f=s?w1:w0;endmodulemodule mux4

21、to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodule测试测试程序程序Test Bench) 要求要求1： 时时延延单单位位为为1ns, 时时延精度延精度为为1ns 2： 单单位位时时延延delay) = 50ns 3: 经过经过1个单个单位位时时延后延后选择选择w1, 4: 经过经过2个单个单位位时时延后延后选择选择w3, 5: 经过经过4

22、个单个单位位时时延后延后选择选择w2, 6: 经过经过6个单个单位位时时延后延后选择选择w0, 7: 经过经过1个单个单位位时时延后延后选择选择w1,timescale 1ns/1nsmodule tb_mux4to1; reg 3:0 w; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w(w), .s(s), .f(f); initial begin w=4b0101; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*6) s=2b00; #

23、(DELAY*1) s=2b01; #(DELAY*30) $finish; endendmodulemodule mux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmoduleModelSim时时序仿序仿真结真结果果图图498 选选 1 选选 择择 器器 (RTL)508选选1选择选择器的器的Verilog HDL编编程程1module m

24、ux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodulemodule mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f=s?w1:w0;endmodulemodule mux8to1 (w,s,f); input 7:0 w; input 2:0 s; output f;

25、wire 1:0 M; mux4to1 mux1 (w3:0,s1:0,M0); mux4to1 mux2 (w7:4,s1:0,M1); mux2to1 mux3 (M1:0,s2,f);endmodule518选选1选择选择器的器的测试测试程序程序timescale 1ns/1nsmodule tb_mux8to1; reg 7:0 w; reg 2:0 s; wire f; parameter DELAY=50;mux8to1 M8to1 (.w(w), .s(s), .f(f); initial begin w=8b00110101; s=3b010; #DELAY s=3b011;

26、#DELAY s=3b001; #DELAY s=3b101; #DELAY w=8b1100010; s=3b001; #DELAY s=3b010; #DELAY s=3b100; #DELAY s=3b110; #DELAY w=8b10111001; s=3b101; #DELAY w=8b11000011; s=3b100; #DELAY s=3b100; #(DELAY*30) $finish; endendmodulemodule mux8to1 (w,s,f); input 7:0 w; input 2:0 s; output f; wire 1:0 M; mux4to1 mu

27、x1 (w3:0,s1:0,M0); mux4to1 mux2 (w7:4,s1:0,M1); mux2to1 mux3 (M1:0,s2,f);endmodule52ModelSim 时时序仿序仿镇结镇结果果536 选选 1 选选 择择 器器546选选1选择选择器的器的Verilog HDL程序程序module mux6to1(w,s,f); input 5:0w; input 2:0 s; output reg f; always(w,s) if(s=3b000) f=w0; else if(s=3b001) f=w1; else if(s=3b010) f=w2; else if(s=3

28、b011) f=w3; else if(s=3b100) f=w4; else if(s=3b101) f=w5; else f=f;endmoduleRTL (Register Transfer Level) 存存放器放器传输级传输级566选选1选择选择器的器的Quartus2时时序仿序仿真真576选选1选择选择器的器的测试测试程序程序timescale 1ns/1nsmodule tb_mux6to1; reg 5:0 w; reg 2:0 s; wire f;mux6to1 M_6to1 (.w(w), .s(s), .f(f);initial begin s=3b000; w=6b00

29、0001; #50 s=3b001; w=6b000100; #50 s=3b010; w=6b000110; #50 s=3b011; w=6b100110; #50 s=3b100; w=6b010001; #50 s=3b101; w=6b011111; #50 s=3b110; w=6b111111; #150 s=3b111;endendmodulemodule mux6to1(w,s,f); input 5:0w; input 2:0 s; output reg f; always(w,s) if(s=3b000) f=w0; else if(s=3b001) f=w1; else

30、 if(s=3b010) f=w2; else if(s=3b011) f=w3; else if(s=3b100) f=w4; else if(s=3b101) f=w5; else f=f;endmoduleModelSim时时序仿序仿真结真结果果图图5916选选1选择选择器的器的Verilog HDL编编程程1： 5个个4选选1选择选择器器2： 2个个8选选1选择选择器器 + 1个个2选选1选择选择器器3： 15个个2选选1选择选择器器6016选选1选择选择器的器的Verilog HDL编编程程module mux16to1 (w, s, f); input 15:0 w; input

31、3:0 s; output f; wire 3:0 m; mux4to1 Mux1 (w3:0, s1:0, m0); mux4to1 Mux2 (w7:4, s1:0, m1); mux4to1 Mux3 (w11:8, s1:0, m2); mux4to1 Mux4 (w15:12, s1:0, m3); mux4to1 Mux5 (m3:0, s3:2, f);endmoduleRTL (Register Transfer Level) 存存放器放器传输级传输级62多多 路路 选选 择择 器器 (1)w1w2f000011101110真值真值表表:f = W1 W2f = W1 W2+逻

32、辑逻辑函函数数:63多多 路路 选选 择择 器器 (2)w1w2f000011101110真值真值表表:01f0001w14by1 mux 图图形符形符号号101101w264多多 路路 选选 择择 器器 (3)w1w2f000011101110真值真值表表:w1f0w21w2If (w1 = 0) f = w2;else f = w2 65多多 路路 选选 择择 器器 (4)真值真值表表:w1f0w21w2w0w1f01If (w1 = 0) f = w2;else f = w2 664选选1多路器多路器来实现来实现三三输输入表入表决决器器真值真值表表:w1w2w3f000000100100

33、01111000101111011111w1w2f00001w310w31110w3f1w1w267译译 码码 器器Decoder68译码译码器器 (n-to-m decoder)- 在数字系统当中在数字系统当中, 离散的情报量可以由二进制离散的情报量可以由二进制(binary)数来表示数来表示- 实践上实践上, ASIC运用领域当中译码器运用领域当中译码器(decoder)是最多运用的是最多运用的- n位数的二进制数输入信号可以转换为位数的二进制数输入信号可以转换为 个不同的输出信号个不同的输出信号- 译码器译码器 - - Decoder - - n-to-m 译码器译码器 (m = ) -

34、 dec2to4, dec3to8 n2n269n位输入位输入 位输出位输出 译码器译码器 .Wn-1EnW0.Y012nyn位位输输入入使能使能(enable)n2位位输输出出binary decodernton2n2702到到4 译码译码器器 (2-to-4 decoder)真值真值表表:W0W1EnY0Y1Y2Y3图图形符形符号号EnW1W0Y3Y2Y1Y010000011010010110010011110000XX0000712 到到 4 译译 码码 器器 的的 逻逻 辑辑 电电 路路W1Y0Y1Y2Y3W0En逻辑电逻辑电路路真值真值表表:EnW1W0Y3Y2Y1Y01000001

35、1010010110010011110000XX0000722到到4译码译码器的器的Verilog HDL 编编程程(1)真值真值表表:module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmoduleEnW1W0Y3Y2Y1Y0100000110

36、10010110010011110000XX0000732到到4译码译码器的器的Verilog HDL编编程程(2)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (En = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmodulemodule dec2to4 (W, En, Y); input 1:

37、0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmodule742到到4译码译码器的器的Verilog HDL编编程程(3)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (E

38、n = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmodulemodule dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; integer k; always (W, En) for (k = 0; k = 3; k = k+1) if (W = k) & (En = 1) Yk = 1; else Yk = 0;endmodule752到到4 译码译

39、码器的器的时时序仿序仿真真(Quartus II)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmoduleRTL (Register Transfer Level) : 存放器存放器传输级传输级76分析分析时时序仿序仿真结真结果果772到

40、到4 译码译码器的器的时时序仿序仿真真 (2)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (En = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmoduleRTL:782到到4 译码译码器的器的时时序仿序仿真真 (3)module dec2to4 (W, En, Y); input 1:0 W;

41、 input En; output reg 3:0 Y; integer k; always (W, En) for (k = 0; k B; AgtB = 1,A B) AgtB = 1; else AltB = 1; endendmodule4 位位 算算 术术 比比 较较 器器 的的 RTL4 位位 算算 术术 比比 较较 器器 的的 时时 序序 仿仿 真真 begin AeqB = 0; AgtB = 0; AltB = 0; if (A = B) AeqB = 1; else if (A B) AgtB = 1; else AltB = 1; end132移移 位位 器器Shift

42、Register133 移移 位位 器器 (Shift Register)输输入信入信号号:向右挪向右挪动动1位位:Clock:?DCB输输出信出信号号:输输入信入信号号:输输出信出信号号:MSBLSB?D DCBADCBA134 移移 位位 器器 (Shift Register)shift : 控制信控制信号号W : w3 w2 w1 w0: 4位位输输入信入信号号Y : Y3 Y2 Y1 Y0: 4位位输输出信出信号号Step 1: If (shift = 1) 向右挪向右挪动动1位位(W);Step 2 Y ?Setp 3: else Y ?Y3 = 0, Y2 = w3, Y1 = w

43、2, Y0 = w1Y = W, k = 0135 移移 位位 器器 的的 逻逻 辑辑 电电 路路 图图1010101010shiftY3Y2Y1Y0k0W3W2W1W00136 移位器移位器(向右向右)的的Verilog HDL编编程程 (1)module shift4 (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y

44、= W; k = 0; end endendmoduleW3W2W1W0Y3 Y2 Y1 Y00W3W2W1k输输入信入信号号:向右挪向右挪动动1位位:输输出信出信号号:137 移位器的移位器的Verilog HDL编编程程 (2)module shifter (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end en

45、dendmodulemodule shift4 (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y = W; k = 0; end endendmodulealways (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin

46、Y = W; k = 0; end end时时序仿序仿真真1时时序仿序仿真真2 always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end endRTLmodule shifter (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin

47、 Y = W; k = 0; end endendmodule时时序仿序仿真真 (clk)3module test (clk, Shift, W, Y, k); input clk, Shift; input 3:0 W; output reg 3:0 Y; output reg k; always (posedge clk) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y = W; k = 0; end endendmodulemodule shifter (clk, W, Shift, Y, k);

48、input clk, Shift; input 3:0 W; output reg 3:0 Y; output reg k; always (posedge clk) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end endendmodule时时序仿序仿真真 (clk)4串型移位器串型移位器 (右初始右初始值值=0A = rtin, A3:1;移位器移位器右右1位位CLK串型串型输输入信入信号号rtin)Clear串型串型输输出信出信号号(A)- - - - 1 0 1 10000 (初始初始100

49、0 (1st)1100 (2nd)0110 (3rd)1011 (4th)串型移位器串型移位器 (右的分解右的分解A = rtin, A3:1;3210In210rtinA3:13初始形初始形状状：移位形移位形状状：3102最最终终形形状状：module test (CLK, Clr, rtin, A); input CLK, Clr; / clock and clear input rtin; / serial input output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if

50、(Clr) A = 4b0000; else A = rtin, A3:1; endendmoduleVerilog HDL 编编程程时时序仿序仿真真time simulation)module test (CLK, Clr, rtin, A); input CLK, Clr; / clock and clear input rtin; / serial input output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = 4b0000; else A = rti

51、n, A3:1; endendmodule串型移位器串型移位器 (右右)初始初始值值=datamodule test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = DataIn; else A = rtin, A3

52、:1; endendmodule移位器的移位器的运运用用(bit to byte)CLK串型串型输输入信入信号号Bit)Clear输输出信出信号号(Byte)组组合器合器(记数记数器器,移位器移位器- - 1 0 1 1 1 0 1 1Message Signal10111011- 串型串型输输入入(Bit)- 组组合合8位位数数的的Byte- 1Byte 信信号输号输出出时输时输出出message 信信号号移位器的移位器的运运用用(bit to byte)串型串型输输入信入信号号Bit)输输出信出信号号(Byte)记数记数器器移位器移位器输输出信出信号号(Message)Verilog HD

53、L 编编程程module test (CLK, Clr, Bit, Byte, FirstByteSignal, zBitCnt); input CLK, Clr; input Bit; output 7:0 Byte; output FirstByteSignal; output 3:0 zBitCnt; reg 7:0 Byte; reg FirstByteSignal; reg 3:0 zBitCnt;always (posedge CLK or negedge Clr) begin if (Clr) begin zBitCnt = 4d0; Byte = 8d0; FirstByteS

54、ignal = 1b0; end else begin Byte = Bit, Byte7:1; zBitCnt = zBitCnt + 1b1; if(zBitCnt=4d8) FirstByteSignal = 1b1; else FirstByteSignal = 1b0; end endendmodule时时序仿序仿真真time simulation)输输入信入信号号： 1 1 0 1 1 1 0 1LSBMSB 移位器移位器(向左向左)的的Verilog HDL编编程程 (1)152module shift4 (W, Shift, Y, k); input 3:0 W; input

55、Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y0 = 0; Y3:1 = W2:0; k = W3; end else begin Y = W; k = 0; end endendmoduleW3W2W1W0Y3 Y2 Y1 Y0kW2W10输输入信入信号号:向左挪向左挪动动1位位:输输出信出信号号:W0时时序仿序仿真真1 always (W, Shift) begin if (Shift) begin Y0 = 0; Y3:1 = W2:0; k = W3; end else

56、begin Y = W; k = 0; end end时时序仿序仿真真2 always (W, Shift) begin if (Shift) begin Y = W 1; k = W3; end else begin Y = W; k = 0; end end串型移位器串型移位器 (左左)初始初始值值=0A = A2:0, rtin;移位器移位器右右1位位CLK串型串型输输入信入信号号rtin)Clear串型串型输输出信出信号号(A)- - - - 1 0 1 10000 (初始初始0001 (1st)0011 (2nd)0110 (3rd)1100 (4th)串型移位器串型移位器 (左左)

57、的分解的分解3210In210rtinA2:03初始形初始形状状：移位形移位形状状：3102最最终终形形状状：A = A2:0, rtin;module test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = Da

58、taIn; else A = A2:0, rtin; endendmoduleVerilog HDL 编编程程时时序仿序仿真真module test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = DataIn; e

59、lse A = A2:0, rtin; endendmoduleMemory(存存储储器器Memory存存储储器器MemoryRAM (Random Access Memory) (随随机存取存机存取存储储器器)ROM (Read Only Memory) (只只读读存存储储器器) Digital LogicROMRAMRAMRandom Access Memory)- 可可写写 (Memory Write Operation)- 可可读读 (Memory Read Operation)- bit byte words- 16 bit = 2 byte = 1 wordsRAM的模的模块图块图

60、Memory unitn数数据据输输入入线线(n data input lines)N数数据据输输出出线线(n data output lines)K 地址地址线线(K address lines)读读(Read)写写(Write)例例: 1024 x 16 Memory 内内容容二进制(binary)十进制(decimal)Memory contest000000000001011010101011101000000000111010101110001001000000001020000110101000110111111110110211010001110001100111111111010220