eda实验1指导手册

1、第一个实验e确的操作步骤，其他的不说了，直接主题了:半加器真值衣:abcoso0000010110011110电路:公式：so = ab + abco = ab实验步骤：点file->new project wizard,弹出下图，按page 1 > 2、4、5 of 5,分布设置以卜5个对 话框。点击finish结束。device familyshow in available device listeamily:package:any二|d evices:| max iiz二pin count:anyfiit argej devicespeed grade: |any二|q a

2、uto device selected by the fitterv show advanced devices、specific device selected in 'available devices* list厂 hardcopy compatible onlyselect the family and device you want to target for compilation.available devices:namei core vlesufm bl. |八epm240zm68c6epm240zm68c7epm240zm100c6epm240zm100c7epm5

3、70zm100c6epm570zm100c7epm570zm144c6epm570zm144c7epm570zm256c6878v8v8v8v8v8v8v8vooooooooo444477777222255555-companion devicehardcopy:|p limit dsp & ram to hardcopy device resourcesback next > finish | 取消new project vizard: eda tool settings page 4 of 5specify the other eda toois in addition to

4、 the quartus ii software - used with the project.design entry/synthesistool n ame:<none>format:|厂 run this tool automatically to synthesize the current designsimulationtool name:format:r run gate-level simulation automatically after compilationtiming analysistool name: |<none>format:|厂 r

5、un this tool automatically after compilation< back i| finish取消nev project vizard: su»ary page 5 of 5when you click finish, the project will be created with the following settings:project directory:f:/altera/90/quartu$/work$hop/eda/adder/< backi finish ji取消project name:addert op-level desi

6、gn entity:addernumber of files added:0number of user libraries added:0device assignments:family name:max7000sdevice:autoeda tools:design entry/sy nthesis:<none>simulation:<none>timing analysis:<none>operating conditions:core voltage:n/ajunction temperatureange:n/a在 project navigato

7、r r 中呈现如卜.:entity矗 max7000s: auto adderhierarchy | e) files程 design units ：tasks点” d按钮，出现下列对话框，选择蓝色部分，点ok出现倘./adder.bdf| compilatior点符号 d ,出现下框，并选择primitives库，在name出输入相应的名称，获得元件图后,点击ok,就能在图形输入框中把元件逐个放入。并用 =连线。symbollibraries:0 & f: /altera/90/quarlus/librafie$/ 爭d megafunctions ©g othersisf

8、eicer bulogothpinminame:2 repeat-insert mode 厂 insert symbol as block 厂 launch megawizard plug-inokmegawizard plugn manager.cancel结果如下图 /addet bdfi当出现如下信息,编译成功。quartus iiflow statusquartus ii versionrevi si on nametop-level entity namefull compilation was successful (1 warning)successful 9.0 build a

9、dder adder max7000s yes 2/32 (6 8/36 ( 2： epm7032slj：- final确定在点击ii d ,出现下图，选择蓝色部分，点击ok在右边出现waveforml.vmf文件内容:屆./adder.bdf compation report flow summary0 waveforml.vwf15.2n$4* pointer:6.4inter vat8.8 n$start:vtlu« tt15.2 nsmaster time bar20.0 ns30ns点击。在如下框内鼠标右击，出现insert node or bus,namevalue at

10、15.2 nslllfl：点击node finder按钮,点击list,在nodes found卡屮出现a、b co、so端口，选屮所有，按嵯键，将所有节 点放入selected nodes卡中，点击ok结果如下:选中入口 a,如图呈现天蓝色,namevalue 砒15.2 ns pirva英10aa 0|4ba 0a 2coa xo抄3soa xa且点击左边的 泡i按钮，出现clock对话框，设置period值，重复操作入口 b结果如下:xizxn. y圖./adder.bdfi f. =777 i compilation report flow summaryinterval:152 ns

11、master time bar:)ps1°小20.9 ns15.2nsu pointe匚8.8 nsstart:保存vwf文件二|匕adder丈档ldbirj i ncr em ent al_db1r| adder. vw£ifi保存类型0):assignment->setting->simulator setting, :simulation mode 模式为 functional,为确认 simulation input 为对应 vwf 文件。iory:generaliles.ibraries)e vicejperating settings and con

12、ditionscompilation process settings；da tool settingsm alysis & synthesis setti ng$itter setting$iming analysis sellings assembler)esign assistant；ignaltap ii logic analyzer.ogic an alyzer in terfacesimulator settingsowerplay power analyzer settirigs )sn analyzersimulator settingsselect simulatio

13、 n options.simulation mode:simulation input:functionaladd multiple files.simulation periodq run simulation until all vector stimuli are used end simulation at:| ns 创glitch filtering options:more settings.点击 proccssing->gcncration functional simulation nctlist,注意这个一宦要点，否则出现的结 杲冇错谋，就像课堂上老师犯的错谋一样。出现

14、成功对话框，按确定即可。uartus/vorkshopmts processing tool c (adder'.二 |惜./adder.lquartus iifunctional simulatiori natlist generatiori was successful点击n,开始仿真，结果如下:按确定，查看仿真结果，比较真值表屮数据，看是否匸确。 compdation report flow summary迅 adder, vwfo| ./adder bdfsimulation report = legal notice flow swim ary flow settings s

15、 simulator 寻® summary 昌翼 settings simulation * £1 simulation idu u“ 冒3 messagessinulati on tarefornssimulation mode： functionalmaster time bar:15.2 nsu ponter:11.95 nsinterval:start:cosovalue at15.2 nzj ps10. 0 ns15.2 nsj20.0 ns做元这个部分，如果要把半加器封装成i个模块，可以点击file->creat/update->create sym

16、bol files for current file,弹出如卜对话框，设直默认名保存即可。这样其他原理图就可以调用这 个模块。亦 o c? eba tizr«»4atd. ku4«r uf 甌 u4«rcrrmtr sybbol filr文isywbu file ( bio詁x思flffs d>其值表:ainbincincoutsum0000000101010010111010001101101101011111结果如f：全加器原理图:s«tun<t simulation simulationsibulttion report 昌閤 u(al motict 0口 flow sunmtry flow st times -j siaultlor看sfl xu vstf*注意，在做全加器的时候，编译和仿真前要记得在project nagivator卡屮的file卡屮设置相 应文件为set as top level entity （在文件下，鼠标右击，选此选项），其他的步骤一样，请自 行操作。下次我们还要实现一个四位全加器原理图，请先完成半加器和全加器。如鼠标点击 f_adder.bdf, /x击右键，选 set as top level