集成电路设计—全加器

1、 集成电路设计实践报告 题目: 全加器设计 院系: 自动化与信息工程 专业班级 学生学号: 学生姓名: 指导教师姓名: 职称:_ 起止时间: 2015-1-5到2015-01-14 成绩:_ 一课设基本任务：全加器设计1) 依据全加器的真值表，给出全加器的电路图完成全加器由电路图到晶体管级的转化（需提出至少2种方案）；2) 绘制原理图（Sedit）,完成电路特性模拟（Tspice，瞬态特性），给出电路最大延时时间；3) 遵循设计规则完成全加器晶体管级电路图的版图，流程如下：版图布局规划基本单元绘制功能块的绘制布线规划-总体版图）；4) 版图检查与验证（DRC检查）；5) 针对自己画的版图，给出

2、实现该全加器的工艺流程图。二、电路设计方案原理:三个输入位：数据位A 和B，低位进位输入Ci 二个输出位：全加和S，进位输出Co真值表ABC iSC o0000000110010100110110010101011100111111根据一位全加器的输入输出关系得:得电路图： 方案一:传输门一位全加器优点：晶体管使用数目少缺点：电路功耗大方案二：互补静态CMOS实现的全加器优点：静态功耗小缺点：晶体管数目多，占硅片面积大，延迟时间高3 电路特性仿真及分析1).电路图2) .电路图网表* SPICE netlist written by S-Edit Win32 7.03* Written on

3、Jan 10, 2015 at 22:57:48* Waveform probing be.options probefilename="Module1.dat"+ probesdbfile="C:UsersASUSDesktop集成电路实践tannerS-EditMYB3110433031.sdb"+ probetopmodule="Module0".lib "C:UsersASUSDesktop集成电路实践ic_techfilescz6h+_v20.lib" tt* Main circu

4、it: Module0M1 Co N2 Vdd Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM2 Co N2 Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M3 N2 A N12 Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM4 N6 B Vdd Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM5 N5 A Gnd Gnd NENH L=0.35u W=0.7

5、u AD=66p PD=24u AS=66p PS=24u M6 N2 A N16 Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M7 N5 B Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M8 N16 B Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M9 N2 Ci N5 Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M10 N2 Ci N6

6、Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM11 N12 B N6 Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM12 N6 A Vdd Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM13 N19 N2 N1 N1 NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M14 N1 A Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66

7、p PS=24u M15 N1 B Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M16 N1 Ci Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M17 N19 Ci N10 Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M18 N10 A N22 Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M19 N22 B Gnd Gnd NENH L=0.

8、35u W=0.7u AD=66p PD=24u AS=66p PS=24u M20 SUM N19 Gnd Gnd NENH L=0.35u W=0.7u AD=66p PD=24u AS=66p PS=24u M21 N9 Ci Vdd Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM22 N9 A Vdd N4 PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM23 N9 B Vdd N7 PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM2

9、4 N19 N2 N9 Vdd PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM25 N13 B N11 N14 PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM26 N19 Ci N13 N14 PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM27 N11 A N9 N14 PENH L=0.35u W=1.4u AD=66p PD=24u AS=66p PS=24uM28 SUM N19 Vdd Vdd PENH L=0.35u W=1.4u AD

10、=66p PD=24u AS=66p PS=24uv29 Vdd Gnd 5.0v30 A Gnd pulse(0.0 5. 220n 1n 1n 200n 400n)v31 B Gnd pulse(0.0 5.0 100n 1n 1n 100n 200n)v32 Ci Gnd pulse(0.0 5.0 40n 1n 1n 50n 100n).model PENH PMOS.model NENH NMOS* End of main circuit: Module0VIN IN GND PULSE (0 3.3 0 10n 50n 100n).tran/op 10n 600n method=b

11、df.print tran v(A) v(B) v(Ci) v(SUM) v(Co).end3).TSpice进行仿真4 版图的布局规划及基本单元的设计1).版图2).版图DRC检测3) .版图网表* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;* TDB File: C:UsersacerDesktoplplp.tdb* Cell: Cell0Version 1.18* Extract Definition File: .lpic_techfilesxauteei

12、c_35um.ext* Extract Date and Time: 01/13/2015 - 17:39.probe.options probefilename="C:lp.dat"+ probesdbfile="C:lphpf1.sdb"+ probetopmodule="Module0".lib "C:UsersASUSDesktop集成电路实ic_techfilescz6h+_v20.lib"tt* NODE NAME ALIASES* 2 = A (70.55,7.9)* 3 = S (146.4,-25

13、.15)* 5 = Co (99.25,-30.95)* 6 = GND (70.95,-44)* 7 = VDD (67.15,3.25)* 18 = B (75.15,11.5)* 19 = Ci (83.2,15.4)M1 S 1 VDD VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M1 DRAIN GATE SOURCE BULK (144.7 -23.85 145.05 -21.8) M2 Co 4 VDD VDD PENH L=5.74E-007 W=

14、1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M2 DRAIN GATE SOURCE BULK (100 -29.6 102.05 -29.25) M3 1 4 13 VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M3 DRAIN GATE SOURCE BULK (110.3 -11.95 112.35 -11.6) M4 1 Ci 15 VDD PENH L=5.74E-007

15、 W=1.25E-006 AD=1.375E-012 PD=4.7E-006 AS=1.3125E-012 PS=4.6E-006 * M4 DRAIN GATE SOURCE BULK (126.2 -18 126.55 -15.95) M5 14 A 13 VDD PENH L=5.74E-007 W=1.25E-006 AD=1.375E-012 PD=4.7E-006 AS=1.3125E-012 PS=4.6E-006 * M5 DRAIN GATE SOURCE BULK (122.9 -10.3 123.25 -8.25) M6 15 B 14 VDD PENH L=5.74E-

16、007 W=1.25E-006 AD=1.375E-012 PD=4.7E-006 AS=1.3125E-012 PS=4.6E-006 * M6 DRAIN GATE SOURCE BULK (124.55 -14.15 124.9 -12.1) M7 13 A VDD VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M7 DRAIN GATE SOURCE BULK (116.05 -5.7 118.1 -5.35) M8 13 Ci VDD VDD PENH L

17、=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M8 DRAIN GATE SOURCE BULK (110.35 -5.7 112.4 -5.35) M9 13 B VDD VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M9 DRAIN GATE SOURCE BULK (121.2 -5.7 123.25 -5.35) M10 4 A 16 VDD PEN

18、H L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M10 DRAIN GATE SOURCE BULK (75 -19 75.35 -16.95) M11 4 Ci 17 VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M11 DRAIN GATE SOURCE BULK (81.75 -10.7 82.1 -8.65) M12 16 B 17 VDD PE

19、NH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M12 DRAIN GATE SOURCE BULK (73.35 -14.45 73.7 -12.4) M13 17 A VDD VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M13 DRAIN GATE SOURCE BULK (71.75 -9.05 73.8 -8.7) M14 17 B VDD

20、VDD PENH L=5.74E-007 W=1.25E-006 AD=1.3125E-012 PD=4.6E-006 AS=1.375E-012 PS=4.7E-006 * M14 DRAIN GATE SOURCE BULK (76.4 -9.05 78.45 -8.7) M15 S 1 GND GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M15 DRAIN GATE SOURCE BULK (144.7 -28.35 145.05 -25.9) M16 Co 4

21、GND GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M16 DRAIN GATE SOURCE BULK (95.5 -29.6 97.95 -29.25) M17 10 A 9 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M17 DRAIN GATE SOURCE BULK (132.5 -35.55 132.85 -33.1) M18 9 B

22、 GND GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M18 DRAIN GATE SOURCE BULK (130.9 -40.25 131.25 -37.8) M19 1 Ci 10 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M19 DRAIN GATE SOURCE BULK (134.1 -29.45 134.45 -27) M20 G

23、ND A 8 GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M20 DRAIN GATE SOURCE BULK (110 -30.3 112.45 -29.95) M21 GND Ci 8 GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M21 DRAIN GATE SOURCE BULK (123.05 -30.3 125.5 -29.95) M2

24、2 GND B 8 GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M22 DRAIN GATE SOURCE BULK (116.05 -30.3 118.5 -29.95) M23 8 4 1 GND NENH L=3.5E-007 W=2.45E-006 AD=3.92E-012 PD=8.1E-006 AS=4.165E-012 PS=8.3E-006 * M23 DRAIN GATE SOURCE BULK (110 -25.8 112.45 -25.45) M2

25、4 GND B 11 GND NENH L=4.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.675E-012 PS=7.9E-006 * M24 DRAIN GATE SOURCE BULK (87.15 -32.4 87.6 -29.95) M25 11 A 4 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M25 DRAIN GATE SOURCE BULK (85.65 -28.7 86 -26.25) M26

26、 GND B 12 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M26 DRAIN GATE SOURCE BULK (79.7 -31.45 82.15 -31.1) M27 12 Ci 4 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M27 DRAIN GATE SOURCE BULK (74.75 -26.55 77.2 -26.2) M28 GND A 12 GND NENH L=3.5E-007 W=2.45E-006 AD=4.165E-012 PD=8.3E-006 AS=3.92E-012 PS=8.1E-006 * M28 DRAIN GATE SOURCE BULK (74.75 -31.45 77.2 -31.1) * Total Nodes: 19* Total Elements: 28* Total Number of Shorted Elements not written to the SPICE file: 0* Extract Elapsed Time: 0 sec