EDA数字时钟宁波工建学院verilogpld

1、EDA 课 程 设 计 报 告设计（论文）题目： 多功能数字时钟的设计 学 院 名 称： 电子与信息工程学院 专 业： 电子科学与技术 班 级： 电科102 姓 名： 感谢我吧 学 号 哈哈 小 组 成 员： ok 指 导 教 师： 王 蔚 日期： 2013 年 12 月 18 日一、 简述·························

2、3;·······································二、 设计要求说明·········&

3、#183;···············································2.1设计总体要求

4、3;·················································

5、3;··2.2设计基本要求··············································&

6、#183;······2.3设计提高部分要求·········································&#

7、183;·······三、 系统设计·········································&

8、#183;···················3.1整体设计方案····························

9、3;·························3.2秒脉冲发生电路·······················

10、·····························3.3译码显示电路···················

11、83;··································3.4计时电路 ··············&

12、#183;·······································3.5复位电路·········

13、·················································四、 功能模

14、块电路设计·················································&

15、#183;····4.1秒脉冲发生电路模块···········································&

16、#183;···4.2 整体时钟设计模块············································&

17、#183;····五、 系统调试············································

18、·················5.1 系统调试·······························

19、3;·························5.11消抖电路调试·······················

20、······························5.12计时电路调试··················&#

21、183;··································5.13 秒产生电路调试·············&#

22、183;······································5.14整点报时电路调试·········&#

23、183;·········································5.15 数码显示电路调试 ······

24、···········································5.16 时校时电路调试 ·····

25、;············································5.17 状态灯电路调试 ···

26、3;·············································5.2 管脚分配···&#

27、183;·················································&#

28、183;···六、 参考文献·············································&

29、#183;···············七、 实验感想·································

30、····························摘要：本次EDA课程设计利是在QuartusII软件平台上用verilog硬件语言来编程设计PLD电路，最终设计出一简单的数字时钟电路，并且将程序代码烧写到EDA试验箱进行验证。本次设计充分采用了软件编程中分层次、模块化的编程思想，同时也充分考虑到了硬件结构编程与

31、纯软件编程的差异性，仿真与实际烧写相结合，逐步完善其逻辑、功能。本系统主要由时钟基本功能电路、闹钟电路、动态显示控制电路、分频电路，状态灯显示电路，按键电路组成，实现了时分秒的计时、闹钟报时，整点报时，调整时分等功能。关键字：数字时钟 ；模块化；分层思想；硬件结构Abstract:The EDA curriculum design benefit is the software platform on QuartusII verilog hardware design language for programming PLD circuit, the final design of a sim

32、ple digital clock circuit, and the EDA program code into the chamber for verification. The full use of the software program designed hierarchically, modular programming ideas, but also give full consideration to the structure of programming and hardware differences pure software programming, simulat

33、ion and actual programming combined with the gradual improvement of its logic function. The system consists of a basic functional circuit clock, alarm circuits, dynamic display control circuit, divider circuit, display circuit status lights, key circuit, achieved when every minute chronograph, alarm

34、 time, the whole point of time, adjusting hours and other functions.Key word: Digital clock; modular; hierarchical thinking; hardware architecture一、 简述在QuartusII软件平台上使用verilong硬件编程语言设计了简易的数字时钟，该时钟在控制电路的作用下具有保持、清零、快速校时、快速校分、整点报时、闹钟等功能。，可以完成一般的时钟任务。数字计时器的系统框图如下图所示:数字时钟系统结构框图译码显示电路脉冲发生电路计时电路报时电路校时分电路清零

35、电路闹钟电路复用开关电路段位码选择电路数字计时器的硬件电路框图如下图所示:数码管显示控制电路（本次设计的内容）本次设计就是设计这一部分的数字逻辑控制电路轻触按键（自动弹回式）蜂鸣器（报警彩铃）二、 设计要求说明（1）设计总体要求：利用QuartusII软件设计一个数字钟，对设计电路进行功能仿真，并下载到SmartSOPC实验系统中，可以完成00:00:00到23:59:59的计时功能，并在按键控制电路的作用下具有保持、清零、快速校时、快速校分、整点报时、闹钟等功能，做到能够创新的添加自己能够实现的功能。（2）设计基本要求1进行正常的时、分、秒计时功能。2分别由六个数码管显示时、分、秒的计时。3

36、有系统使能开关4有系统清零开关5有系统校分开关6.有系统校时开关（3）设计提高部分要求1使时钟具有整点报时功能2闹表设定功能3自己添加其他功能（4）已经完成的设计完成了进行正常的时、分、秒计时功能，能够通过数码管正常显示时、分、秒的计时，能够实现闹钟的设定以及闹醒功能，同时支持整点报时。按键设计上由于试验箱上8个按键完全足够使用，不需要按键复用，大大简化了按键扫描电路的设计，具体分配如下K0是系统的清零开关K0=0正常工作，K0=1时钟清零K1是系统的使能开关K1=0正常工作，K1=1时钟保持不变K2是系统的校时开关K2=0正常工作，K2=1时钟进入校时K3是系统的闹钟设置开关K3=0正常工作

37、，K3=1时钟进入闹钟设置K4是系统的时 （单位）加按键K4=0正常工作，K4=1时钟时加一K5是系统的分 （单位）加开关K5=0正常工作，K5=1时钟分加一三、 系统设计3.1整体设计方案多功能数字计时器是由计时电路、译码显示电路、脉冲发生电路和控制电路等几部分基本电路组成的，其中控制电路按照设计要求可以由校时电路、清零电路、报时电路和闹钟设计电路等组成。多功能数字钟控制器的系统框图如下图所示：多功能数字钟控制器系统结构图译码显示电路脉冲发生电路计时电路报时电路校对电路清零电路闹钟电路控制电路原则确定的思路：首先需要考虑到的是此次设计要实现的功能有：正常的计时、保持、清零、校时、校分以及整点

38、报时功能；闹铃功能，从使用者的角度来看闹铃需要设定相应的校分、校时功能； 其次需考虑控制电路的设计有以下一些要求：1. 考虑到有8个按键，按键数量完全能够满足本系统设计要求，不采用按键复用技术，简化编程步骤，方便使用者的操作，不易出错具有便捷的特点2. 按键的干扰，充分考虑完善按键消抖的过程，防止误操作3. 闹钟设定模块、正常时钟模块的切换不影响时钟的正常计时；3.2整体设计算法流程开始模式判断处理按键，执行操作3.3译码显示模块一般的显示分为两种，即静态显示与动态显示；所谓静态显示，即每一个数码管由单独的七段显示译码器驱动，如要显示N位字符，必须用N个七段显示译码器，这种现实方法极大地浪费了

39、芯片的控制管脚。动态显示则是利用了数据选择器的分时复用功能，将任意多位数码管的显示驱动，由一个七段显示译码器来完成。这样即节省了器件及芯片管脚，又提高了元件的使用效率。在此次实验中，我们采用了动态显示的方法，利用八进制计数器分别实现对秒个位、秒十位、分个位、分十位、时个位、时十位利用一个六进制计数器实现扫描，扫描到的显示管的位选信号为1同时相应段码信号同时传到七段显示。扫描频率设置为1KHz，这样躲过人眼的辨别范围，使得肉眼看上去与静态显示没有什么区别。译码显示结构图：段选位选数码管显示模块CLK 1ms8位 时钟数据输入 8位3.4计时电路计时电路用的是1hz的时钟信号输入，从秒的个位开始分

40、别开始自加1，直到秒信号累计到六十，开始进位至分钟的个位，一次类推一直到小时的十位。分别采用模60至模24 的计数方式，实现计时功能。计时电路结构图：3.5 清零电路复位电路采用k0开关来控制，实现的功能则是，当该键被按下之后，就可以实现计时清零功能。清零电路结构图：具体的参见上计时电路中的流程框图3.5 脉冲发生电路分频电路（时钟分频，为数码管，按键蜂鸣器等提供时钟信号）48MHZ脉冲信号 1HZ 1KHZ 500HZ3.6 校时校分流程3.6 闹钟判断流程四、 功能模块电路设计此次设计一共有以下几个模块：正常显示模块、分频模块闹铃设定模块、闹铃比较模块、显示管段选模块、显示管位选模块；为了

41、写代码方便都放在一个module 里，只将分频单独隔离出来。4.1秒脉冲发生电路模块module make_sec(clk,out_clk1hz);input clk;output out_clk1hz;reg sec;reg 24:0 count1; /定义计数器always (posedge clk) /定义clock上升沿触发begincount1 = count1 + 1'b1;if(count1 = 25'd24000000)/判断0.5Sbegincount1 = 25'd0;/计数器清零sec = sec;/置位秒标志endendassign out_cl

42、k1hz=sec; /秒输出endmodule4.2 整体时钟模块module clock(clk,clk1h,key,dig,seg,modestateled,bsbeep);/模块名clockinput clk;input clk1h;/输入时钟input5:0 key;/输入按键output7:0dig;/数码管选择输出引脚output7:0 seg;/数码管段码output2:0 modestateled;/模式灯output bsbeep;/蜂鸣器输出reg 7:0seg_r; /数码管段输出引脚reg 7:0dig_r; /数码管位输出引脚reg3:0 disp_dat;/定义显示

43、数据寄存器reg24:0count;/定义计数寄存器reg 24:0hour,jzhour,nzhour;/定义时钟，闹钟，校时寄存器reg sec,keyen,bsbeep_r,zdbeep_r;/定义秒信号，乒乓开关，蜂鸣器寄存器reg2:0 modestate;/定义状态模式reg5:0dout1,dout2,dout3;/寄存器reg27:0zdcount;/定义整点计时器wire5:0key_done;/定义按下后稳定的键值wire bsbeep;assign dig = dig_r;/输出数码管选择assign seg = seg_r;/输出数码管译码结果/各类触发信号always

44、 (posedge clk) /定义clock上升沿触发beginif(count = 25'd24000000)/0.5S到了吗？begincount = 25'd0;sec=sec; end /计数器清零else begin count = count + 1'b1; endend/按键消抖处理部分assign key_done = (dout1 | dout2 | dout3);/按键消抖输出always (posedge count17)begindout1 <= key;dout2 <= dout1;dout3 <= dout2;endalw

45、ays (negedge key_done1)/计数开关beginkeyen = keyen;end/按键输入工作模式led显示处理部分assign modestateled = modestate;/令状态可以用灯输出always (key_done)/工作模式beginif(key_done3:1=3'b110) begin modestate = 3'b110;/计时模式 end else if(key_done3:1=3'b101)/校时模式 begin modestate = 3'b101; end else if(key_done3:1=3'

46、b011)/闹钟模式 begin modestate = 3'b011; end else if (key_done3:1=3'b001) modestate=3'b001;end/数码管动态扫描显示部分always (posedge clk) /count17:15大约1ms改变一次begincase(count17:15)/选择扫描显示数据3'd0:disp_dat = hour3:0;/秒个位3'd1:disp_dat = hour7:4;/秒十位3'd2:disp_dat = 4'ha;/显示"-"3'

47、d3:disp_dat = hour11:8;/分个位3'd4:disp_dat = hour15:12; /分十位3'd5:disp_dat = 4'ha;/显示"-"3'd6:disp_dat = hour19:16; /时个位3'd7:disp_dat = hour23:20; /时十位endcasecase(count17:15)/选择数码管显示位3'd0:dig_r = 8'b11111110;/选择第一个数码管显示3'd1:dig_r = 8'b11111101;/选择第二个数码管显示3&#

48、39;d2:dig_r = 8'b11111011;/选择第三个数码管显示3'd3:dig_r = 8'b11110111;/选择第四个数码管显示3'd4:dig_r = 8'b11101111;/选择第五个数码管显示3'd5:dig_r = 8'b11011111;/选择第六个数码管显示3'd6:dig_r = 8'b10111111;/选择第七个数码管显示3'd7:dig_r = 8'b01111111;/选择第八个数码管显示endcaseendalways (posedge clk)begincase

49、(disp_dat)4'h0:seg_r = 8'hc0;/显示04'h1:seg_r = 8'hf9;/显示14'h2:seg_r = 8'ha4;/显示24'h3:seg_r = 8'hb0;/显示34'h4:seg_r = 8'h99;/显示44'h5:seg_r = 8'h92;/显示54'h6:seg_r = 8'h82;/显示64'h7:seg_r = 8'hf8;/显示74'h8:seg_r = 8'h80;/显示84'h9:se

50、g_r = 8'h90;/显示94'ha:seg_r = 8'hbf;/显示-default:seg_r = 8'hff;/不显示endcaseif(count17:15= 3'd2)&sec)seg_r = 8'hff;if (count17:15=3'd5)&sec)/数码管秒和分，分和时之间显示“-” seg_r=8'hff;end/校时以及闹钟校时处理部分always (negedge key_done4)beginif(modestate = 3'b101)/计时模式下 begin jzhour1

51、9:16 = jzhour19:16 + 1'b1;/时个位加一 if(jzhour19:16 = 4'ha) beginjzhour19:16 = 4'h0;jzhour23:20 = jzhour23:20 + 1'b1;/时十位加一end if(jzhour23:16 = 8'h24) jzhour23:16 = 8'h0;endif(modestate = 3'b011)/闹钟模式下 begin nzhour19:16 = nzhour19:16 + 1'b1;/时个位加一 if(nzhour19:16 = 4'h

52、a) beginnzhour19:16 = 4'h0;nzhour23:20 = nzhour23:20 + 1'b1;/时十位加一end if(nzhour23:16 = 8'h24) nzhour23:16 = 8'h0;endend/校时分处理部分always (negedge key_done5)beginif(modestate = 3'b101)/校时模式 begin jzhour11:8 = jzhour11:8 + 1'b1;/分个位加一 if(jzhour11:8 = 4'ha) beginjzhour11:8 = 4&

53、#39;h0;jzhour15:12 = jzhour15:12 + 1'b1;/分十位加一 end if(jzhour15:8 = 8'h60) jzhour15:8 = 8'h0; endif(modestate = 3'b011)/闹钟模式 begin nzhour11:8 = nzhour11:8 + 1'b1;/分个位加一 if(nzhour11:8 = 4'ha) beginnzhour11:8 = 4'h0;nzhour15:12 = nzhour15:12 + 1'b1;/分十位加一 end if(nzhour15

54、:8 = 8'h60) nzhour15:8 = 8'h0; endend/计时处理部分always (posedge sec or negedge key_done0)/计时处理beginif(!key_done0)/是清零键吗？beginhour = 24'h0; /是，则清零endelse if(modestate = 3'b101)/是校对时间模式吗？ hour=jzhour;/是的话则让显示时间为校时的时间else if (modestate = 3'b011)/is alarm state? hour=nzhour;/是的话则让显示时间为闹钟

55、的时间else if(!keyen)&&(modestate = 3'b110)|(modestate=3'b011)/是计时间模式吗？beginhour3:0 = hour3:0 + 1'b1;/秒加1if(hour3:0 = 4'ha)beginhour3:0 = 4'h0;hour7:4 = hour7:4 + 1'b1;/秒的十位加一if(hour7:4 = 4'h6)beginhour7:4 = 4'h0;hour11:8 = hour11:8 + 1'b1;/分个位加一if(hour11:8 =

56、 4'ha)beginhour11:8 = 4'h0;hour15:12 = hour15:12 + 1'b1;/分十位加一if(hour15:12 = 4'h6)beginhour15:12 = 4'h0;hour19:16 = hour19:16 + 1'b1;/时个位加一if(hour19:16 = 4'ha)beginhour19:16 = 4'h0;hour23:20 = hour23:20 + 1'b1;/时十位加一endif(hour23:16 = 8'h24)hour23:16 = 8'h0

57、;endendendendendend/闹钟歌曲reg yqbeep_r;/寄存器reg7:0 state;/乐谱状态机reg15:0count1,count_end;reg23:0count2;/乐谱参数:D=F/2K (D:参数,F:时钟频率,K:音高频率)parameter L_5 = 16'd61224, /低音5L_6 = 16'd54545,/低音6M_1 = 16'd45863,/中音1M_2 = 16'd40865,/中音2M_3 = 16'd36402,/中音3M_5 = 16'd30612,/中音5M_6 = 16'd

58、27273,/中音6H_1 = 16'd22956;/高音1parameterTIME = 12000000;/控制每一个音的长短(250ms)always(posedge clk)begincount1 <= count1 + 1'b1;/计数器加1if(count1 = count_end)begincount1 <= 16'h0;/计数器清零yqbeep_r <= !yqbeep_r;/输出取反endendalways (posedge clk)beginif(count2 < TIME)/一个节拍250mScount2 = count2

59、+ 1'b1;elsebegincount2 = 24'd0;if(state = 8'd147)state = 8'd0;elsestate = state + 1'b1;case(state)8'd0,8'd1:count_end = L_5;/低音"5",持续2个节拍8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8: count_end = M_1;/中音"1",持续7个节拍8'd9,8'd10:cou

60、nt_end = M_3;/中音"3",持续2个节拍8'd11,8'd12,8'd13,8'd14: count_end = M_2;8'd15: count_end = M_1;8'd16,8'd17: count_end = M_2;8'd18,8'd19: count_end = M_3;8'd20,8'd21,8'd22,8'd23,8'd24: count_end = M_1;8'd25,8'd26: count_end = M_3;8&

61、#39;d27,8'd28: count_end = M_5;8'd29,8'd30,8'd31,8'd32,8'd33: count_end = M_6;8'd34,8'd35,8'd36,8'd37,8'd38: count_end = M_6;8'd39,8'd40,8'd41,8'd42: count_end = M_5;8'd43,8'd44,8'd45: count_end = M_3;8'd46,8'd47: count_

62、end = M_1;8'd48,8'd49,8'd50,8'd51: count_end = M_2;8'd52: count_end = M_1;8'd53,8'd54: count_end = M_2;8'd55,8'd56:count_end = M_3;8'd57,8'd58,8'd59,8'd60: count_end = M_1;8'd61,8'd62,8'd63: count_end = L_6;8'd64,8'd65: count_en

63、d = M_5;8'd66,8'd67,8'd68,8'd69:count_end = M_1;8'd70,8'd71,8'd72,8'd73: count_end = M_1;8'd74,8'd75: count_end = M_6;8'd76,8'd77,8'd78,8'd79: count_end = M_5;8'd80,8'd81,8'd82: count_end = M_3;8'd83,8'd84: count_end = M_1;8

64、'd85,8'd86,8'd87,8'd88: count_end = M_2;8'd89: count_end = M_1;8'd90,8'd91: count_end = M_2;8'd92,8'd93: count_end = M_6;8'd94,8'd95,8'd96,8'd97:count_end = M_5;8'd98,8'd99,8'd100: count_end = M_3;8'd101,8'd102: count_end = M_5;

65、8'd103,8'd104,8'd105,8'd106:count_end = M_6;8'd107,8'd108,8'd109,8'd110: count_end = M_6;8'd111,8'd112: count_end = H_1;8'd113,8'd114,8'd115,8'd116: count_end = M_5;8'd117,8'd118,8'd119: count_end = M_3;8'd120,8'd121: count_

66、end = M_1;8'd122,8'd123,8'd124,8'd125: count_end = M_2;8'd126: count_end = M_1;8'd127,8'd128: count_end = M_2;8'd129,8'd130: count_end = M_3;8'd131,8'd132,8'd133,8'd134: count_end = M_1;8'd135,8'd136,8'd137: count_end = L_6;8'd138,8

67、'd139: count_end = M_5;8'd140,8'd141,8'd142,8'd143:count_end = M_1;8'd144,8'd145,8'd146,8'd147: count_end = M_1;default:count_end = 16'h0;endcaseendend/整点报时处理部分assign bsbeep=bsbeep_r;always(posedge clk)beginif(modestate = 3'b110)&&(hour15:0>=4&#

68、39;h0000)&&(hour15:0<=4'h0005)bsbeep_r=zdbeep_r; /蜂鸣器输出为整点报时 else if(modestate=3'b110)&&(nzhour23:8=hour23:8)bsbeep_r=yqbeep_r; /蜂鸣器输出为闹钟输出else bsbeep_r=1'b0; end/整点滴滴处理部分always(posedge clk)beginzdcount <= zdcount + 1'b1;endalways (zdcount9)/计时第十位，让其产生半秒的滴答声begi

69、nzdbeep_r = !(zdcount13&zdcount24&zdcount27);end endmodule 输入输出模块框图 图4.2.1模块输入输出图 逻辑图 图4.2.2 整体输入输出逻辑图 图4.2.3 秒计数器门电路原理图 图4.2.4 小时计数器原理图五、 系统调试 5.1系统调试 5.11按键消抖仿真调试1、 仿真代码timescale 1ns/1nsmodule anjianxiaodou_tp;reg clk1ms,key,dout1,dout2,dout3;wire key_done,dout1o,dout2o,dout3o;parameter DE

70、LY=100;always #(DELY/2) clk1ms=clk1ms;anjianxiaodou u1(key_done,clk1ms,key,dout1o,dout2o,dout3o);initial begin clk1ms=0;key=1; #DELY key=0; #DELY key=0; #DELY key=0;#(DELY*20); # DELY $finish;endinitial $monitor($time,"key_done=%b dout1=%b dout2=%b dout3=%b key=%b",key_done,dout1o,dout2o,d

71、out3o,key);endmodulemodule anjianxiaodou(key_done,clk1ms,key,dout1o,dout2o,dout3o);input key,clk1ms;output key_done;reg dout1,dout2,dout3;output dout1o,dout2o,dout3o;assign dout1o=dout1;assign dout2o=dout2;assign dout3o=dout3;always (posedge clk1ms)begindout1 <= key;dout2 <= dout1;dout3 <=

72、dout2;endassign key_done = (dout1 | dout2 | dout3);/按键消抖输出endmodule2、仿真波形 图5.1按键消抖3、 分析 一个按键按下之后测试在三个十周中期内是否被按下，如果保持，这说明是被确实按下。5.12 计时模块仿真1、 仿真代码： timescale 1ns/1nsmodule jishichuli_tp;reg reset,clk;wire 23:0hourout;parameter DELY=100;always #(DELY/2) clk=clk;jishichuli u1(clk,reset,hourout);initial begin clk=0;reset=0;#DELY reset=1;#DELY reset=0;#(DELY*300);# DELY $finish;endinitial $monitor ($time," hourout=%b",hourout);endmo