硬件描述语言第九讲

1、硬件描述语言及器件 教材：任勇峰等编著vhdl与硬件实现速成 主讲教师：刘文怡08/09学年第1学期教学安排n第1讲：vhdl概述及其开发环境 n第2讲：vhdl的基本元素 n第3讲：vhdl的进程 n第4讲：其它并行语句 n第5讲：vhdl实例剖析 n第6讲：vhdl的顺序描述语句 n第7讲：结构体的描述风格 n第8讲：计数器状态控制n第9讲：不同风格的状态机设计n第10讲：vhdl综合举例第9讲：不同风格的状态机设计n1 上节内容回顾n2 计数值与状态的关系n3 递变型状态变更控制n4 状态机使用n5 两种不同类型的状态机1 上节内容回顾n时序逻辑时序逻辑n复位的概念与功用、同步复位和异步

2、复位复位的概念与功用、同步复位和异步复位n计数器设计、利用计数值控制状态变更计数器设计、利用计数值控制状态变更n时序逻辑电路又称为同步电路，基础电路包括触发器、寄时序逻辑电路又称为同步电路，基础电路包括触发器、寄存器、计数器。存器、计数器。n由数字电路知道，任何时序电路都以时钟为驱动信号，时由数字电路知道，任何时序电路都以时钟为驱动信号，时序电路只是在时钟信号的边沿到来时，其状态才发生改变。序电路只是在时钟信号的边沿到来时，其状态才发生改变。因此，时钟信号是时序电路程序的执行条件，时钟信号是因此，时钟信号是时序电路程序的执行条件，时钟信号是时序电路的同步信号。时序电路的同步信号。n什么是时钟？

3、其作用是什么？什么是时钟？其作用是什么？复位，设定初始状态n时序电路的初始状态应由复位信号来设置。根据复位信号时序电路的初始状态应由复位信号来设置。根据复位信号对时序电路复位的操作不同，使其可以分为同步复位和异对时序电路复位的操作不同，使其可以分为同步复位和异步复位。步复位。n所谓异步复位，就是当复位信号有效时，时序电路立即复所谓异步复位，就是当复位信号有效时，时序电路立即复位，与时钟信号无关。位，与时钟信号无关。同步复位process (clock)beginif clock =1 and clockevent thenif reset = 1 then sout = 0; tmp = 0;

4、elsesout = sin;tmp = not tmp;end if; end if;end process;sinclockresetsouttmp异步复位process (clock, reset)beginif reset = 1 thensout = 0;tmp = 0;elsif clock =1 and clockevent thensout = sin; tmp = not tmp;end if;end process;sinclockresetsouttmp可逆计数器n可逆计数器根据计数脉冲的不同，控制计数器在同步信号可逆计数器根据计数脉冲的不同，控制计数器在同步信号脉冲的作

5、用，进行加脉冲的作用，进行加1操作，或者减操作，或者减1操作。操作。nclr1时，计数器清零；时，计数器清零；n可逆计数器的计数方向，由特殊的控制端可逆计数器的计数方向，由特殊的控制端updn控制。控制。n当当updn = 1时，计数器加时，计数器加1操作；操作；n当当updn = 0时，计数器减时，计数器减1操作；操作； clkclrupdnqnlibrary ieee；nuse ieee.std_logic_1164.all；nuse ieee.std_logic_unsigned.all；nentity count isn port (clk，clr，updn: in std_logic

6、；n q: out std_logic_vector(7 downto 0);nend count；narchitecture example of count isn signal count_b:std_logic_vector (7 downto 0);nbeginn q = count_b; n process (clr，clk)n beginn if(clr=1) then n count_b=“00000000”;n elsif (clkevent and clk= 1 ) thenn if (updn=1) then n count_b=count_b + 1;n else n

7、count_b=count_b 1;n end if；n end if;n end process;nend example;用计数器值做条件来控制时序nprocess (clr，clk)nbeginnif(clr=1) then n count_b=“00000000”;nq = 0;nelsif (clkevent and clk= 1 ) thenncount_b=count_b + 1;nif (count_b = “00000000”) then n q = 1;nelsif (count_b = “00000001”) then n q = 0;nelsif (count_b =

8、“00000011”) then n q = 1;nelsif (count_b = “00000100”) then n q = 0;nend if;nend if;nend process;nprocess (clr，clk)nbeginnif(clr=1) then n count_b=“00000000”;nq = 0;nelsif (clkevent and clk= 1 ) thennif (count_b = “00001111”) then ncount_b=“00000000”;nelsencount_b=count_b + 1;nif (count_b = “0000000

9、0”) then n q = 1;nelsif (count_b = “00000001”) then n q = 0;nelsif (count_b = “00000011”) then n q = 1;nelsif (count_b = “00000100”) then n q = 0;nend if;nend if;nend if;nend process;调整周期用计数值控制产生精确时序n只要知道晶振频率f，即可知道周期t1/f；n使用一个计数器，可以通过计数值n，精确知道当计数值为n时消耗的时间tnt；n上例中以n为控制条件，可以控制其它信号在某时刻变高，某时刻变低，从而产生精确时序

10、；n但要注意：时间分辨率（或叫最小控制时间间隔）取决于晶振频率。分频器nsignal count : std_logic_vector(7 downto 0)； nprocess ( fosc，rst)nbeginnif rst = 1 thenncount = “00000000”;nq = 0;nelsif foscevent and fosc=1 thennif count = 00000010 thenncount = 00000000;nq = not q;nelsencount = count +1;nend if; nend if;nend process;2 计数值与状态的关系

11、nprocess (clr，clk)nbeginnif(clr=1) then n count_b=“00000000”;nq = 0;nelsif (clkevent and clk= 1 ) thennif (count_b = “00001111”) then ncount_b=“00000000”;nelsencount_b=count_b + 1;nif (count_b = “00000000”) then n q = 1;nelsif (count_b = “00000001”) then n q = 0;nelsif (count_b = “00000011”) then n

12、q = 1;nelsif (count_b = “00000100”) then n q = 0;nend if;nend if;nend if;nend process;特点 n随着clk的推进，计数器独立运转，不受各状态的支配；n计数器的每一计数值都可以用来对应不同的状态，这些状态都会遍历到，即使很多数值未出现，它也是存在的；n计数值的顺序决定了各状态发生的次序，这一次序是确定的；n计数的最大值决定了状态是有限的；n不同状态间的时间间隔是确定的，精确的；n具有明显的周期性。clk计数器状态变更nprocess (clr，clk)nbeginnif(clr=1) then n count_b

13、=“00000000”;nq = 0;nelsif (clkevent and clk= 1 ) thenn-if (count_b = “00001111”) then n-count_b=“00000000”;n-elsen- count_b=count_b + 1;nif (count_b = “00000000”) then n q = 1; count_b = “00000001”;nelsif (count_b = “00000001”) then n q = 0; count_b = “00000010”;nelsif (count_b = “00000010”) then n

14、count_b = “00000011”;nelsif (count_b = “00000011”) then n q = 1; count_b = “00000100”;nelsif (count_b = “00000100”) then n q = 0; count_b = ?;nend if;nend if;nend if;nend process;更改一下 对比nif (count_b = “00001111”) then ncount_b=“00000000”;nelsencount_b=count_b + 1;nif (count_b = “00000000”) then n q

15、= 1;nelsif (count_b = “00000001”) then n q = 0;nelsif (count_b = “00000011”) then n q = 1;nelsif (count_b = “00000100”) then n q = 0;nend if;nend if;nif (count_b = “00000000”) then n count_b = “00000001”; q = 1; nelsif (count_b = “00000001”) then n count_b = “00000010”; q = 0; nelsif (count_b = “000

16、00010”) then n count_b = “00000011”;- ?nelsif (count_b = “00000011”) then n count_b = “00000100”; q = 1; nelsif (count_b = “00000100”) then n count_b = ?; q -code state:=101;when 101 = state:=110; -code;when 110 = state:=100; -code;when 100 = state:=011; -code;when 011 = state:=010; -code;when 010 =

17、 state:=000; -code;when others= state:=000; -code;end case;end if;end process;end arc; 000101110100011010特点n上例实际上也可以看成计数器，是广义的计数器，计数值和次数由设计者保证；n如果值不连续，则不成其为计数器，只是状态递变；n如果在某一状态下，根据条件对下一个状态做了分支，则逻辑趋于复杂：ncase state isnwhen 000 = nif x=1 thennstate:=101;nelsenstate:=“110”;nend ifnwhen “001” = 状态值的问题 n人为

18、手工设置数值的方法具有局限性，容易重复、误写；人为手工设置数值的方法具有局限性，容易重复、误写；n一种较好的方法是定义常量，一次定义，任意使用，如：一种较好的方法是定义常量，一次定义，任意使用，如：nconstant st1: std_logic_vector(2 downtoconstant st1: std_logic_vector(2 downto 0):=“001”; 0):=“001”; nconstant st2: std_logic_vector(2 downtoconstant st2: std_logic_vector(2 downto 0):=“010”; 0):=“010

19、”;nconstant st3: std_logic_vector(2 downtoconstant st3: std_logic_vector(2 downto 0):=“011”; 0):=“011”;nconstant st4: std_logic_vector(2 downtoconstant st4: std_logic_vector(2 downto 0):=“100”; 0):=“100”;nwhen “when “010” =state:=“010” =state:=“011”;011”; when when st2 =statest2 =state:=st3;:=st3;n事

20、实上，事实上，vhdlvhdl提供了一种更好的方法，专门定义状态序列，提供了一种更好的方法，专门定义状态序列，那就是枚举类型：那就是枚举类型：枚举类型定义状态机 n定义方式：定义方式：type 名称名称 is (元素元素1,元素元素2);n举例：举例：ntype week is (mon, tue, wed, thu, fri, sat, sun); ntype std_logic is (u,x,0,1,z,w,l,h,-); ntype states is (state0,state1,state2,state3); 状态机样例 ntype wr is (wr0,wr1,wr2,wr3,w

21、r4,wr5); - 结构级别结构级别nsignal state: wr; - 结构级别结构级别n复位时赋初始状态复位时赋初始状态 state state state statestate state = wr0;nend case;4 状态机使用带复位的状态机architecture arc of ss istype states is (st0,st1,st2,st3);signal outc: states;beginprocess(clk) begin if reset=1 then outc outc outc outc outc outc if x=1 then state:=00

22、1; else state:=100; end if; when 001 = if x=1 then state:=011; else state:=000; end if; when 011 = when others= if x=1 then state:=000; else state:=000; end if; end case;end if; opif x = 0 thennext_state = s0;elsenext_state = s1;end if;op if x = 0 thennext_state = s3;elsenext_state = s2;end if;op if x = 0 thennext_state = s2;elsenext_state = s3;end if;op if x = 0 thennext_state = s3;elsenext_state = s0;end if; op = 0; end case;end process state_comp; process (clk)beginif clkevent and clk = 1 thenpresent_state if x = 0 thennext_state = s0;elsenext_state = s1;end if;if x = 0 thenop = 0;elseo