EDA实验报告波形生

1、2009-2010第一学期北京工业大学实验学院EDA实验报告题 目 波形发生与嵌入式逻辑分析仪 专 业 电子信息工程 学 号 07521203 姓 名 马艳 成 绩 指导教师 2009年 12 月 6 日一 实验目的学习内嵌式逻辑分析工具Signal TabII测试波形功能。达到检验设计效果和提高分析设计过程的能力。二 实验内容与要求利用内嵌式逻辑分析工具完成信号发生器设计及编译、综合、适配、仿真和硬件测试，能够产生正弦波，方波，三角波，锯齿波。三 实验平台（1）硬件：计算机、GX-SOC/SOPC-DEVLAB CycloneII EP2C35F672C8核心扳（2）软件：Quartus I

2、I四 实验原理 嵌入式逻辑分析仪主要分为硬件部分和软件部分。硬件部分由待测设计（DUT），嵌入到FPGA中的ELA IP核、RAM存储单元以及JTAG接口组成；软件部分由用户设计软件和集成在其中的ELA在线调试软件组成。五 程序代码-clkgen.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY clkgen IS PORT(clkin:IN STD_LOGIC ; clkout: OUT STD_LOGIC);END;ARCHITECTURE even OF clkgen IS

3、constant N:Integer:=16; SIGNAL coun:integer range 0 to N; SIGNAL clk1:STD_LOGIC;BEGIN PROCESS(clkin) BEGIN IF(clkin'EVENT AND clkin='1')THEN IF(coun=N)THEN coun<=0; clk1<=Not clk1; else coun<=coun+1; END IF; END IF; END PROCESS; clkout<=clk1; END even;-方波library ieee; use iee

4、e.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fang2 is port( clk : in std_logic; fd1 : out std_logic_vector(7 downto 0); end; ARCHITECTURE fang OF fang2 IS SIGNAL q:integer range 0 to 1;BEGINPROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN q&

5、lt;=q+1; END IF; END PROCESS; process(q) begin case q is when 0=>fd1<="00000000" when 1=>fd1<="11111111" when others=>null; end case; end process; end architecture;-三角波library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned

6、.all;entity sanj isport(clk: in std_logic; dd3 : out std_logic_vector(7 downto 0) );end;architecture one of sanj isbeginprocess(clk) variable num : std_logic_vector(7 downto 0);variable ff : std_logic;beginif (clk'event and clk='1') then if ff = '0' then if num="11111000&quo

7、t;then num:="11111111" ff:='1' else num:=num+8; end if; else if num="00000111" then num:="00000000" ff:='0' else num:=num-8; end if; end if; end if; dd3<=num; end process;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;entity jvchi2 is port(clk,up_down:

8、in std_logic; dd2:out integer range 255 downto 0); end; architecture one of jvchi2 is signal d,temp:integer range 255 downto 0; begin process(clk) begin if(clk'event and clk='1') then if temp<198 then temp<=temp+2; else temp<=0; end if; end if; end process; process(temp,up_down)

9、 begin if up_down='0' then d<=temp; else d<=198-temp; end if; end process; dd2<=d; end;六 引脚定义及代码代码：# Copyright (C) 1991-2008 Altera Corporation# Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions,

10、 and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agree

11、ment, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details.# Quartus II:

12、Generate Tcl Project# File: wave.tcl# Generated on: Thu Nov 12 12:00:52 2009# Load Quartus II Tcl Project packagepackage require :quartus:projectset need_to_close_project 0set make_assignments 1# Check that the right project is openif is_project_open if string compare $quartus(project) "wave&qu

13、ot; puts "Project wave is not open"set make_assignments 0 else # Only open if not already openif project_exists wave project_open -revision wave wave else project_new -revision wave waveset need_to_close_project 1# Make assignmentsif $make_assignments set_global_assignment -name FAMILY &qu

14、ot;Cyclone II"set_global_assignment -name DEVICE EP2C35F672C8set_global_assignment -name TOP_LEVEL_ENTITY wavetopset_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.0set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:58:59 NOVEMBER 12, 2009"set_global_assignment -name LAST_

15、QUARTUS_VERSION 8.0set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palaceset_global_assignment -name DEVICE_FILTER_PACKAGE FBGAset_global_assignment -name DEVICE_FILTER_PIN_COUNT 672set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8set_global_assignment -name

16、MIN_CORE_JUNCTION_TEMP 0set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Topset_global_assignment -name PARTITION_COLOR 14622752 -section_id Topset_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"s

17、et_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"set_global_assignment -name BDF_set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top# Commit assignmentsexport_assignmentsset_location_assignment PIN_B13 -to clkset_location_assignm

18、ent PIN_F6 -to switch0set_location_assignment PIN_A21 -to switch1set_location_assignment PIN_B21 -to switch2set_location_assignment PIN_J25 -to dac_abset_location_assignment PIN_J26 -to dac_csset_location_assignment PIN_U26 -to dac_wrset_location_assignment PIN_G21 -to dout0set_location_assignment PIN_E23 -to dout1set_location_assignment PIN_E24 -to dout2set_location_assignment PIN_B24 -to dout3set_location