数电实验报告

1、一，实验结果分析实验一：Quartus II 原理图输入法设计（2） 实验名称：设计实现全加器实验任务要求：用实验内容（1）中生成的半加器模块和逻辑门设计实现一个全加器，仿真并验证其功能，并下载到实验板测试，要求用拨码开关设定输入信号，发光二极管显示输出信号。原理图：仿真波形图：仿真波形图分析：输入a,b代表加数与被加数，输入c代表低位向本位的进位。输出s代表本位和，输出co代表向高位的进位。可得真值表为：abcsco0000000110010100110110010101011100111111与上边的仿真波形图对比可知电路设计正确。实验三：用VHDL设计与实现时序逻辑电路（3） 实验名称：

2、连接8421计数器，分频器和数码管译码器实验任务要求：用VHDL语言设计实现一个带异步复位的8421码十进制计数器，分频器的分频系数为25k，并用数码管显示数字。VHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity div isport(clk1 : in std_logic; clk_out : out std_logic);end;architecture d of div issignal cnt : integer range 0 to 12499999;signal

3、 clk_tmp : std_logic;beginprocess(clk1)beginif (clk1'event and clk1='1') thenif cnt=12499999 thencnt<=0;clk_tmp<= not clk_tmp;elsecnt<=cnt+1;end if;end if;end process;clk_out<=clk_tmp;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count10

4、IS PORT( clk2,clear2:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count10;ARCHITECTURE count OF count10 IS SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk2,clear2) BEGIN IF clear2='1' THEN q_temp<="0000" ELSIF (clk2'event AND clk2='1') THEN IF q_

5、temp="1001" THEN q_temp<="0000" ELSE q_temp<=q_temp+1; END IF; END IF; END PROCESS; q<=q_temp;END count;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY seg7 IS PORT(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b: OUT STD

6、_LOGIC_VECTOR(6 DOWNTO 0); cat1:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); END seg7;ARCHITECTURE show OF seg7 IS BEGIN PROCESS(a) BEGIN CASE a IS WHEN"0000"=>b<="1111110" WHEN"0001"=>b<="0110000" WHEN"0010"=>b<="1101101" WHEN"

7、0011"=>b<="1111001" WHEN"0100"=>b<="0110011" WHEN"0101"=>b<="1011011" WHEN"0110"=>b<="1011111" WHEN"0111"=>b<="1110000" WHEN"1000"=>b<="1111111" WHEN

8、"1001"=>b<="1111011" WHEN OTHERS=>B<="0000000" END CASE; END PROCESS; cat1<="111011"END show; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jishuqi8421 is port(clk,clear:IN STD_LOGIC; cout:OUT STD_LOGIC_VECTOR(6

9、 DOWNTO 0); cat:OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );end jishuqi8421;architecture ji of jishuqi8421 iscomponent div25m port(clk1 : in std_logic; clk_out : out std_logic);end component;component count10 PORT( clk2,clear2:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);end component;component seg7 PORT

10、(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); cat1:OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );end component; signal c:std_logic; signal d:std_logic_vector(3 downto 0); begin u1:div port map(clk1=>clk,clk_out=>c); u2:count10 port map(clk2=>c,clear2=>clear,q=>d); u3:s

11、eg7 port map(a=>d,b=>cout,cat1=>cat);end ji;仿真波形图：（由于实际使用的50000000分频不方便仿真，仿真时使用12分频）仿真波形图分析：每隔12个时钟信号计数器的值会增加1，直到计数器的值为9时，再次返回0计数。端口说明及连接图：输入端口：clk：输入时钟信号。 clear:输入复位信号。输出端口：cat5-cat0：控制哪个数码管亮。 cout6-cout0：控制数码管的哪一部分亮。实验四：用VHDL实现相关电路（1） 实验名称：用VHDL语言设计并实现六个数码管串行扫描电路实验任务要求：要求同时显示0,1,2,3,4,5这6

12、个不同的数字图形到6个数码管上，仿真验证其功能，并下载到实验板测试。VHDL代码:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shumakongzhi is port(clk_in: in std_logic; cat:out std_logic_vector(5 downto 0); a_out:out std_logic_vector(6 downto 0);end shumakongzhi;architecture a of shumakongzhi issignal tm

13、p:std_logic_vector(6 downto 0); signal cnt:integer range 0 to 599; signal cat_tmp:std_logic_vector(5 downto 0) ; begin process(clk_in) begin if(clk_in'event and clk_in='1') then if cnt=99 then cat_tmp<="011111" cnt<=cnt+1; elsif cnt=199 then cat_tmp<="101111"

14、 cnt<=cnt+1; elsif cnt=299 then cat_tmp<="110111" cnt<=cnt+1; elsif cnt=399 then cat_tmp<="111011" cnt<=cnt+1; elsif cnt=499 then cat_tmp<="111101" cnt<=cnt+1; elsif cnt=599 then cat_tmp<="111110" cnt<=0; else cnt<=cnt+1; end if;

15、end if; case cat_tmp is when"011111"=>tmp<="1111110" when"101111"=>tmp<="0110000" when"110111"=>tmp<="1101101" when"111011"=>tmp<="1111001" when"111101"=>tmp<="0110011" w

16、hen"111110"=>tmp<="1011011" when others=>tmp<="0000000" end case; end process; cat<=cat_tmp; a_out<=tmp; end a;仿真波形图：仿真波形图分析：cati为0时，第i个数码管亮。仿真时使cat5-cat0依次为0且每次只有一个为0。cat5为0时显示0，cat4为0时显示1，cat3为0时显示2，cat2为0时显示3，cat1为0时显示4，cat1为0时显示5。当扫描频率足够大时，就可以看到六个数

17、码显示管同时显示，从左到右依次为012345。端口说明及连接图：输入：clk_in:输入时钟信号。输出：cat5-cat0:控制哪个数码管亮。 a_out6-a_out0:控制数码管的哪一部分亮。（2） 实验名称：用VHDL语言设计并实现六个数码管滚动显示电路实验任务要求：向左滚动，用全灭的数码管填充右边直至全部变灭，然后再依次从右边一个一个地点亮。状态为:0012345->12345X->2345XX->345XXX->45XXXX->5XXXXX->XXXXXX->XXXXX0->XXXX01->XXX012->XX0123-&g

18、t;X01234->012345。VHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY shumasaomiao3 IS PORT(CLK:IN STD_LOGIC; SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); BT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END shumasaomiao3;ARCHITECTURE ACE OF shumasaomiao3 IScomponent fen2kport(clk_in

19、:in std_logic; clk_out:out std_logic);end component; SIGNAL CNT6:INTEGER RANGE 0 TO 11; SIGNAL A:INTEGER RANGE 0 TO 11; SIGNAL COUNT:INTEGER RANGE 0 TO 4999 := 0;SIGNAl FLAG:INTEGER RANGE 0 TO 12 := 0; SIGNAl FLAG_A:INTEGER RANGE 0 TO 11;SIGNAL clk_tmp:STD_LOGIC;BEGINu1:fen2k port map(clk_in=>CLK

20、,clk_out=>clk_tmp);P1:process(CNT6) BEGIN CASE CNT6 IS WHEN 0 => BT <= "011111" ; A <= 0 ; WHEN 1 => BT <= "101111" ; A <= 1 ; WHEN 2 => BT <= "110111" ; A <= 2 ; WHEN 3 => BT <= "111011" ; A <= 3 ; WHEN 4 => BT <=

21、"111101" ; A <= 4 ; WHEN 5 => BT <= "111110" ; A <= 5 ; WHEN 6 => BT <= "111111" ; A <= 6 ; WHEN 7 => BT <= "111111" ; A <= 7 ; WHEN 8 => BT <= "111111" ; A <= 8 ; WHEN 9 => BT <= "111111" ; A &l

22、t;= 9 ; WHEN 10 => BT <= "111111" ; A <= 10 ; WHEN 11 => BT <= "111111" ; A <= 11 ; WHEN OTHERS => NULL; END CASE ;END PROCESS P1;P2:process(clk_tmp)BEGIN IF clk_tmp'EVENT AND clk_tmp= '1' THEN if CNT6= 11 then CNT6<= 0; else CNT6<=CNT6 + 1;

23、 end if; IF (FLAG = 12) THEN FLAG <= 0; END IF; IF COUNT =4999 THEN COUNT <= 0; FLAG <=FLAG+1; ELSE COUNT <=COUNT+1; END IF;END IF;END PROCESS P2; P3:process(A,FLAG,FLAG_A)BEGIN FLAG_A<=( A + FLAG )mod 12); CASE FLAG_A IS WHEN 0=> SG <= "1111110" WHEN 1=> SG <= &

24、quot;0110000" WHEN 2=> SG <= "1101101" WHEN 3=> SG <= "1111001" WHEN 4=> SG <= "0110011" WHEN 5=> SG <= "1011011" WHEN 6=> SG <= "0000000" WHEN 7=> SG <= "0000000" WHEN 8=> SG <= "0000000" WHEN 9=> SG <= "0000000" WHEN 10=> SG <= "0000000" WHEN 11=> SG <= "0000000" WHEN OTHERS =>NULL ; END CASE ;END PROCESS P3; END ACE;仿真波形图：仿真