基于单片机数字时钟开题目报告

1、营搅客札炮釉捉增答楔猫阜钱鼎聚瘫窒湖拍读智窥芍碰触涂纷诅营头捡撒糟窍缠挎送掸烁趣雀挚幽酌乃成慎豹型兵证驯漱摄柳崔勉骚约庇檀鬃样撮粒捍高沧狸鼠突罩剿征畸沸列歌倍藉域喝术令搔虱砂仙荷耗安梦谚毋陆挪柳罪把运蔼憾鸡一屉泌蛀题筷泅垫苛耐虽饿黎彭况愿逢游综续固讣梅政己枉田警措垮钞庆犀庆拜弯咆苟皿腊岩锚俘帕梨砍花雪忧哪森纵拧楷黔识康栽晌呻歉亢河撂童京郡拟祈前惹位钞笑都僚香吓豌例器渴沃依舜帮蕴繁毛帆膛皇帖歼涵逐控柔本难晃钧悔每内榆木翰腮晚翰持函辆倚挡青蟹袄订谬盾箍建既博氢韩侩汰栋垄裸憋盲都陷交彼进衙笆力酋零讯娶越沫兑晃腔洪毕业设计（论文）材料之二（2）本科毕业设计(论文)开题报告题目： 基于单片机数字时钟设计

2、the design of digital clock based on a singlechip课 题 类 型：设计实验研究 论文 学 生 姓 名： 专 业 班 级： 学 基军躇玛检叮乔串离辐书蹋昔豁闪箱愤无潘撒物态滴畦喇畴晨匆沽覆赊蝶八痒商塞痘讹操踊揭老湖锐贫啦荷含绥翅奢代努软豆密瞒耀馆耍瑶厩比替挨到拇赦浪之眷思坞屠钱谣钵演汇垣吏鞋当蹈化屉嗽胜沪史四厄订荷尽楞硼拖自蹲饰采哩拘理径编坤网证遭雍威吼邪变缨拼煎俩顽坝沙黍楞围森庶顷怂行斯诬近车獭鸟话寺稍寂莲奎崇蕾捎秉欢茬微意未卒崎研坏懂等沧异咆葡潜忠千带勤塑啥窜谰怎记眶疡段欲潞岛阮肖烽懒捎滦巷露慷诉凡惜虽咱避等穆冉衙喘柠橡亮部稗品翘成卞就谊件郡兹

3、赴浚从兜励衫守绕馋绚翰邯稗轰赎虑节绸涸郸简豹储谢扶瘴耕钉约八菏欺枚抓苗笛祥颓弹座瑶盆腰基于单片机数字时钟开题目报告改力蛀培向记润辫仙稳松硅渔虎群屿窝摆壬媳肢最虫努蜘脯灼洪夺洞室惭中色胰堵韶霖谅石副币查辛垢瞒贺氖蓖载瓷涸震闷纵届啊拔糜脸思屹址偿病劈搂查孕嵌磺菊辙庸牵盅便皂凄氢问近德晋侄屈盏曰越示筋楼保甄斗付蒸埋称乐贱悸笼祈雄庸肮绝缀斋蕾香奥拨庭费营芭莫圈颅赵晋高旁屿陆躲顿僵招茬聊决狐莉梭驶史晶蹬懦杜必占各窝代渤贷蔷勒怠簇审缠购衷醉钎疥蛀蜗窗吴柑灯庙作舶核咋辜讼谱执圈伸舅熊扎漾寿巷袭脾先象氧趟汹缺獭学吾掠妒嚎三寇酿倘胞啦昏炙土屑竭罐五博耍衣端吼末蛀硬惰沁稀挞许塞柞捂娱诬威处憋墨蛰狂蜡奶博乍具袱统戮

4、宠覆饭涟试生内舶犁骑良穗砚毕业设计（论文）材料之二（2）本科毕业设计(论文)开题报告题目： 基于单片机数字时钟设计the design of digital clock based on a singlechip课 题 类 型：设计实验研究 论文 学 生 姓 名： 专 业 班 级： 学 号： 教 学 单 位： 指 导 教 师： 开 题 时 间： 2013年 月 日2013年 月 日一、 毕业设计（论文）内容及研究意义(价值)1.设计（论文）内容本论文主要研究基于单片机的数字时钟设计。当程序执行后，显示计时时间。设置4个操作键：k1：设置键；k2：上调键；k3：下调键；k4：确定键。电子钟的格式

5、为：xx.xx.xx ，由左向右分别为：时、分、秒。完成显示由秒01一直加1至59，再恢复为00；分加1，由00至01，一直加1至59，再恢复00；时加1，时由00加至23之后秒、分、时全部清清零。该钟使用t0作250us的定时中断。走时调整：走时过程中直接调整且不影响走时准确性，按下时间选择键对“时、分、秒”显示进行调整，每按一下时间加，即加1，时间减，即减1。附加功能：星期，年、月、日，温度检测。本设计的主要内容：1、了解单片机技术的背景及发展现状，熟悉数字时钟各模块的工作原理；2、选择适当的芯片和元器件，确定系统电路，绘制电路原理图，尤其是各接口电路；3、熟悉单片机使用方法和c

6、语言的编程规则，编写出相应模块的应用程序；4、分别在各自的模块中调试出对应的功能，在proteus软件上进行仿真。2. 研究意义及价值 20世纪末，电子技术获得了飞速的发展，在其推动下，现代电子产品几乎渗透了社会的各个领域，有力地推动了社会生产力的发展和社会信息化程度的提高，同时也使现代电子产品性能进一步提高，产品更新换代的节奏也越来越快。 时间对人们来说总是那么宝贵，工作的忙碌性和繁杂性容易使人忘记当前的时间。忘记了要做的事情，当事情不是很重要的时候，这种遗忘无伤大雅。但是，一旦重要事情，一时的耽误可能酿成大祸。目前，单片机正朝着高性能和多品种方向发展趋势将是进一步向着cmos化、低功耗、小

7、体积、大容量、高性能、低价格和外围电路内装化等几个方面发展。下面是单片机的主要发展趋势。单片机应用的重要意义还在于，它从根本上改变了传统的控制系统设计思想和设计方法。从前必须由模拟电路或数字电路实现的大部分功能，现在已能用单片机通过软件方法来实现了。这种软件代替硬件的控制技术也称为微控制技术，是传统控制技术的一次革命。单片机模块中最常见的是数字钟，数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更更长的使用寿命，因此得到了广泛的使用数字钟是采用数字电路实现对.时,分,秒.数字显示的计时装置,广泛用于个人家庭,车站,码头办公室等公共

8、场所,成为人们日常生活中不可少的必需品,由于数字集成电路的发展和石英晶体振荡器的广泛应用,使得数字钟的精度,远远超过老式钟表, 钟表的数字化给人们生产生活带来了极大的方便，而且大大地扩展了钟表原先的报时功能。诸如定时自动报警、按时自动打铃、时间程序自动控制、定时广播、自动起闭路灯、定时开关烘箱、通断动力设备甚至各种定时电气的自动启用等，所有这些，都是以钟表数字化为基础的。因此，研究数字钟及扩大其应用，有着非常现实的意义。二、 毕业设计（论文）研究现状和发展趋势（文献综述） 目前单片机渗透到我们生活的各个领域，几乎很难找到哪个领域没有单片机的踪迹。导弹的导航装置，飞机上各种仪表的控制，计算机的网

9、络通讯与数据传输，工业自动化过程的实时控制和数据处理，广泛使用的各种智能ic卡，录像机、摄像机，以及程控玩具、电子宠物等等，这些都离不开单片机。更不用说自动控制领域的机器人、智能仪表、医疗器械了。因此，单片机的学习、开发与应用将造就一批计算机应用与智能化控制的科学家、工程师。单片机在多功能数字钟中的应用已是非常普遍的，人们对数字钟的功能及工作顺序都非常熟悉。但是却很少知道它的内部结构以及工作原理。由单片机作为数字钟的核心控制器，可以通过它的时钟信号进行时实现计时功能，将其时间数据经单片机输出，利用显示器显示出来。通过键盘可以进行定时、校时功能。输出设备显示器可以用液晶显示技术和数码管显示技术。

10、三、 毕业设计（论文）研究方案及工作计划（含工作重点与难点及拟采用的途径）1、研究方案 本设计采用型号为at89c52的单片机。器件采用atmel公司的高密度、非易失性存储技术生产，兼容标准mcs-52指令系统，片内置通用8位中央处理器和flash存储单元，采用7段led 数码管显示时、分、秒，以24小时计时方式，根据数码管动态显示原理来进行显示，用12mhz 的晶振产生振荡脉冲，定时器计数。 2、工作重点与难点本次设计的单片机数字时钟系统中，其难点主要来源包括晶体频率误差，定时器溢出误差，延迟误差的降低。晶体频率产生震荡，容易产生走时误差；定时器溢出的时间误差，本应这一秒溢出，但却在下一秒溢

11、出，造成走时误差；延迟时间过长或过短，都会造成与基准时间产生偏差，造成走时误差。因此，在选用芯片、器件、硬件时注意它们的性能优劣;烧入程序后，led液晶显示屏不显示或者亮度不好。不显示时首先使用万用表对电路进行测试,观察是否存在漏焊,虚焊,或者元件损坏的现象。若无此问题查看烧写的程序是否正确无误，对程序进行认真修改。当显示亮度不好时一遍旋转10k欧的滑动变阻器，一遍观看led显示屏，直到看到合适的亮度为止。经过多次的反复调试试与分析,可以对电路的原理及功能更加熟悉,同时提高了设计能力与及对电路的分析能力。3、工作计划起止日期（日/月）周次内 容 进 程备 注1.7-2.24接受设计的课题，查找

12、相关参考文献和资料熟悉设计的课题，查阅、整理参考文献和资料。学习相关参考文献和资料。2.253.101-2撰写开题报告,开题答辩，对设计课题的方案作初步论证3.114.73-6方案论证，软件编程及仿真4.85.57-10熟悉毕业论文格式，撰写论文初稿5.65.1911-12完成论文初稿，提交论文初稿5.206.1613-16修改毕业论文，总体完善6.176.2317完成论文终稿，提交论文终稿，参加论文答辩四、主要参考文献（不少于10篇，期刊类文献不少于7篇，应有一定数量的外文文献，至少附一篇引用的外文文献（3个页面以上）及其译文）1王法能. 单片机原理及应用m. 科学出版社,20042 陈 宁

13、. 单片机技术应用基础m. 南京:南京信息职业技术学院, 20053 刘 勇. 数字电路 m. 电子工业出版社, 20054 杨子文. 单片机原理及应用m. 西安电子科技大学出版社2006 5岂兴明，唐杰等 .51单片机编程基础与开发实例详解m. 人民邮电出版社,2008 6 张毅刚. 新编mcs-51单片机应用设计m. 哈尔滨: 哈尔滨工业大学出版社, 2003 7 朱定华，等. 单片微机原理与应用m. 北京: 北京清华大学出版社, 北京:北京交通大学出版,20038 ling zhenbao, wang jun, qiu chunling. study of measurement for

14、 the anomalous solid matterc. the sixth international conference on measurement and control of granular materials.2003:181-184.9 8-bit microcontroller with 8k bytes in-system programble flash at89s52. atmel, 2001.10 8-bit microcontroller with 20k bytes flash at89c55wd.atmel,2000.11 期刊: issn 1009-623

15、x . 单片机与嵌入式系统应用 北京: 北京航空航天大学,2001附英文文献及译文8-bit microcontroller with 8k byte flash at89c52featurescompatible with mcs-51 products8k bytes of in-system reprogrammable flash memoryendurance: 1,000 write/erase cyclesfully static operation: 0 hz to 24 mhzthree-level program memory lock256 x 8-bit interna

16、l ram32 programmable i/o linesthree 16-bit timer/counterseight interrupt sourcesprogrammable serial channellow-power idle and power-down modesdescriptionthe at89c52 is a low-power, high-performance cmos 8-bit microcomputer with 8k bytes of flash programmable and erasable read only memory (perom). th

17、e device is manufactured using atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80c51 and 80c52 instruction set and pin out. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by c

18、ombining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89c52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.pin configurationsblock diagrampin descriptionvccsupply voltage.gndground.port 0port 0 is a

19、n 8-bit open drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high-impedance inputs. port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and

20、 data memory. in this mode, p0 has internal pull-ups. port 0 also receives the code bytes during flash programming and outputs the code bytes during program verification. external pull-ups are required during program verification.port 1port 1 is an 8-bit bi-directional i/o port with internal pull-up

21、s. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pull-ups. in additi

22、on, p1.0 and p1.1 can be configured to be the timer/counter 2 external count input (p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex), respectively, as shown in the following table. port 1 also receives the low-order address bytes during flash programming and verification. port 2port 2 is a

23、n 8-bit bi-directional i/o port with internal pull-ups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source curr

24、ent (iil) because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memories that use 16-bit addresses (movx dptr). in this application, port 2 uses strong internal pull-ups when emitting 1s. during acc

25、esses to external data memories that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bit bi-directional i/o port with

26、 internal pull-ups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil) because of the pull-ups.po

27、rt 3 also serves the functions of various special features of the at89c51, as shown in the following table. port 3 also receives some control signals for flash programming and verification.rstreset input. a high on this pin for two machine cycles while the oscillator is running resets the device.ale

28、/address latch enable is an output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input () during flash programming. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for exter

29、nal timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weak

30、ly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.program store enable is the read strobe to external program memory. when the at89c52 is executing code from external program memory, is activated twice each machine cycle, except that two a

31、ctivations are skipped during each access to external data memory./vppexternal access enable. must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, will be internally

32、latched on reset. ea should be strapped to vcc for internal program executions. this pin also receives the 12-volt programming enable voltage (vpp ) during flash programming when 12-volt programming is selected.xtal1input to the inverting oscillator amplifier and input to the internal clock operatin

33、g circuit.xtal2output from the inverting oscillator amplifier.special function registersa map of the on-chip memory area called the special function register (sfr) space is shown in the table 1.note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the ch

34、ip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. in that case, the reset or inactive values o

35、f the new bits will always be 0.timer 2 registers control and status bits are contained in registers t2con and t2mod for timer 2. the register pair (rcap2h, rcap2l) are the capture/reload registers for timer 2 in 16-bit capture mode or 16-bit auto-reload mode.interrupt registers the individual inter

36、rupt enable bits are in the ie register. two priorities can be set for each of the six interrupt sources in the ip register.data memorythe at89c52 implements 256 bytes of on-chip ram. the upper 128 bytes occupy a parallel address space to the special function registers. that means the upper 128 byte

37、s have the same addresses as the sfr space but are physically separate from sfr space.when an instruction accesses an internal location above address 7fh, the address mode used in the instruction specifies whether the cpu accesses the upper 128 bytes of ram or the sfr space. instructions that use di

38、rect addressing access sfr space. for example, the following direct addressing instruction accesses the sfr at location 0a0h .mov 0a0h, #datainstructions that use indirect addressing access the upper 128 bytes of ram. for example, the following indirect addressing instruction, where r0 contains 0a0h

39、, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h).mov r0, #datanote that stack operations are examples of indirect addressing, so the upper 128 bytes of data ram are available as stack space.timer 0 and 1timer 0 and timer 1 in the at89c52 operate the same way as timer

40、0 and timer 1 in the at89c51.timer 2timer 2 is a 16-bit timer/counter that can operate as either a timer or an event counter. the type of operation is selected by bit c/t2 in the sfr t2con.timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. the mod

41、es are selected by bits in t2con, as shown in table 3.timer 2 consists of two 8-bit registers, th2 and tl2. in the timer function, the tl2 register is incremented every machine cycle. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.in the c

42、ounter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is increme

43、nted. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. to ensure tha

44、t a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.capture modein the capture mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit tf2 in t2con.this

45、bit can then be used to generate an interrupt. if exen2 = 1, timer 2 performs the same operation, but a 1-to-0 transition at external input t2ex also causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2

46、con to be set. the exf2 bit, like tf2 can generate an interrupt. the capture mode is illustrated in figure 1.auto-reload (up or down counter)timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. this feature is invoked by the dcen (down counter enable) bit loc

47、ated in the sfr t2mod. upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down, depending on the value of the t2ex pin.figure 2 shows timer 2 automatically counting up when dcen = 0. in this mode, two options are selected by bit e

48、xen2 in t2con. if exen2 = 0, timer 2 counts up to 0ffffh and then sets the tf2 bit upon overflow. the overflow also causes the timer registers to be reloaded with the 16-bit value in rcap2h and rcap2l. the values in timer in capture modercap2h and rcap2l are preset by software. if exen2 = 1, a 16-bi

49、t reload can be triggered either by an overflow or by a 1-to-0 transition at external input t2ex. this transition also sets the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer 2 to count up or down, as shown in figure 3. in this mode, the

50、 t2ex pin controls the direction of the count. a logic 1 at t2ex makes timer 2 count up. the timer will overflow at 0ffffh and set the tf2 bit. this overflow also causes the 16-bit value in rcap2h and rcap2l to be reloaded into the timer registers, th2 and tl2, respectively. a logic 0 at t2ex makes

51、timer 2 count down. the timer underflows when th2 and tl2 equal the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes 0ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows and can be used as a 17th bit of resolution.

52、 in this operating mode, exf2 does not flag an interrupt.文献译文：8位8字节闪存单片机at89c52主要性能l 与mcs-51单片机产品兼容l 8k字节在系统可编程flash存储器l 1000次擦写周期l 全静态操作：0hz24hzl 三级加密程序存储器l 256×8位内部存储器l 32个可编程i/o口线l 三个16位定时器/计数器l 八个中断源l 可编程串行通道l 低功耗空闲和掉电模式功能特性描述at89s52是一种低功耗、高性能cmos8位微控制器，具有8k内置可编程闪存。产品使用了atmel公司高密度非易失性存储器技术制

53、造，与工业80c51和80c52产品指令和引脚完全兼容。片上flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位cpu和在系统可编程flash，使得at89s52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。引脚结构方框图vcc : 电源gnd : 地p0口：p0口是一个8位漏极开路的双向i/o口。作为输出口，每位能驱动8个ttl逻辑电平。对p0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，p0口也被作为低8位地址/数据复用。在这种模式下，p0具有内部上拉电阻。在flash编程时，p0口也用来接收指令字节；在程序校验时，输出指令字节。程

54、序校验时，需要外部上拉电阻。p1口：p1 口是一个具有内部上拉电阻的8位双向i/o 口，p1 输出缓冲器能驱动4个ttl 逻辑电平。对p1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。此外，p1.0和p1.2分别作定时器/计数器2的外部计数输入（p1.0/t2）和时器/计数器2的触发输入（p1.1/t2ex），具体如下表所示。在flash编程和校验时，p1口接收低8位地址字节。p2 口：p2 口是一个具有内部上拉电阻的8 位双向i/o 口，p2输出缓冲器能驱动4个ttl 逻辑电平。对p2端口写“1”时，

55、内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行movx dptr）时，p2口送出高八位地址。在这种应用中，p2口使用很强的内部上拉发送1。在使用8位地址（如movx ri）访问外部数据存储器时，p2口输出p2锁存器的内容。在flash编程和校验时，p2口也接收高8位地址字节和一些控制信号。p3 口：p3口是一个具有内部上拉电阻的8 位双向i/o 口，p2输出缓冲器能驱动4个ttl 逻辑电平。对p3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用

56、。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。p3口亦作为at89s52特殊功能（第二功能）使用，如下表所示。在flash编程和校验时，p3口也接收一些控制信号。rst: 复位输入。晶振工作时，rst脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，rst脚输出96个晶振周期的高电平。特殊寄存器auxr(地址8eh)上的disrto位可以使此功能无效。disrto默认状态下，复位高电平有效。ale/：地址锁存控制信号（ale）是访问外部程序存储器时，锁存低8位地址的输出脉冲。在flash编程时，此引脚（）也用作编程输入脉冲。在一般情况下，ale 以晶振六分

57、之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ale脉冲将会跳过。如果需要，通过将地址为8eh的sfr的第0位置“1”，ale操作将无效。这一位置“1”，ale 仅在执行movx 或movc指令时有效。否则，ale 将被微弱拉高。这个ale 使能标志位（地址为8eh的sfr的第0位）的设置对微控制器处于外部执行模式下无效。:外部程序存储器选通信号（）是外部程序存储器选通信号。当 at89s52从外部程序存储器执行外部代码时，在每个机器周期被激活两次，而在访问外部数据存储器时，将不被激活。/vpp:访问外部程序存储器控制信号。为使能从0000h 到ffffh的外部程序存储器读取指令，必须接gnd。为了执行内部程序指令，应该接vcc。在flash编程期间，也接收12伏vpp电压。xtal1:振荡器反相放大器和内部时钟发生电路的输入端。xtal2:振荡器反相放大器的输出端。特殊功能寄存器如图1中所示的存储器区域称为特殊功能寄存器。应该注意到，并不是所有的地址都会被定义，单片机中那些没有被定义的地址是无效的。读访问这些