eda整点报时时钟设计

1、eda 技术应用课程设计报告题目名称：多功能数字钟专业班级：姓名 ：学号 ：小组成员：指导教师：设计时间：15-12-01 15-12-25一、设计目的1. 使得更加了解 eda的应用2. 熟悉 vhdl的编程。3. 对于编程语句的编辑与纠错有较大的提升4. 提升对于设计方面的能力二、设计要求1. 数字钟具有“时”、“分”、“秒”显示功能，其中时功能为24 小时制。2. 数字钟具有校时和校分功能。3. 数字钟具有整点报时功能。三、设计方案通过分别作出秒模块、 分钟模块、小时模块、整点报时模块，导入动态扫描模块，再由其输出到数码管输出。四、模块设计1. 秒程序模块有3输入3输出 reset 为异

2、步清零当没有信号时清零秒模块的计数 setmin 为校分 当有信号时想分模块进一位 daout_a 与 daout_b 为输出的信号分别为秒的高位与低位 enmin 负责向下一个模块进位 clk 为时钟信号2. 分钟程序模块 3输入 3 输出 reset 为异步清零当没有信号时清零分模块的计数 sethour 为校分 当有信号时向时模块进一位 daout_ma 分 daout_mb 为输出的信号分别为分的高位与低位 enhour 负责向下一个模块进位 clk 为时钟信号3. 小时程序模块有2输入 2输出 reset 为异步清零当没有信号时清零时模块的计数clk 为时钟信号 daout_ha d

3、aout_hb 为输出的信号分别为时的高位与低位4. 动态扫描模块 有八个输入端，两个输出端 reset 为异步清零当没有信号时清零时模块的计数 daout 为高位5. 七段译码管模块 有1输入 8输出 s 为用来接收秒分时模块输出的信号 ah 为转化后的信号用来接数码管6. 整点报时模块有5输入2输出 clkspk 为时钟信号 miao_h miao_l fen_h fen_h为从秒模块时模块接收的信号 speak 接蜂鸣器， lamp 接 led作为报时时的闪烁灯五、模块程序1. 秒模块设计（ 60 计时制）library ieee;use ieee.std_logic_1164.all;

4、use ieee.std_logic_unsigned.all;entity shijian isport(reset,clk,setmin:in std_logic;daout_a:out std_logic_vector(7 downto 4);输出高位daout_adaout_b:out std_logic_vector(3 downto 0);输出低位daou_benmin:out std_logic); enmin 是向分位进位信号end shijian;architecture behav of shijian issignal count:std_logic_vector(3 d

5、ownto 0); signal counter:std_logic_vector(3 downto 0);signal carry_out1:std_logic;signal carry_out2:std_logic;beginp1:process(reset,clk)begin 59 秒时的进位信号if reset='0'then 59 秒时的进位信号count<="0000"counter<="0000"若 reset为 0 时，则高、低位异步清零elsif(clk'event and clk='1

6、9;)then否则 clk 为上升沿时if(counter<5)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;end if;carry_out1<='0'若高位counter<5, 低位 count=9 ，则低位清零，高位进一，否则低位进一， 59 秒时的进位信号carry_out1为 0。elseif(count=9)thencount<="0000"counter<="0000&quo

7、t;carry_out1<='1'若高位counter 为 5 时，低位 count=9 ，则高、低位清零，59 秒时的进位信号carry_out1进位为 1。elsecount<=count+1;carry_out1<='0'低位 count 加 1，59 秒时的进位信号carry_out1为 0end if;end if;end if;end process;daout_a(7 downto 4)<=counter;高位赋予daout_adaout_b(3 downto 0)<=count;低位赋予daout_benmin<

8、;=carry_out1 or setmin;程序 59 秒的进位信号或手动给 enmin 进位end behav;2. 分钟模块设计（ 60 制计时） library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port(reset,clk,sethour:in std_logic;daout_ma:out std_logic_vector(7 downto 4);输出高位信号daout_madaout_mb:out std_logic_vector(3 downto 0);

9、输出低位信号daout_mbenhour:out std_logic); enhour 向时位进位信号end fen;architecture behav of fen issignal count:std_logic_vector(3 downto 0); signal counter:std_logic_vector(3 downto 0);signal carry_out1:std_logic 59 分的进位信号 carry_out1 signal carry_out2:std_logic; begin p1:process(reset,clk)beginif reset='0&

10、#39;then count<="0000"counter<="0000"若 reset 为 0 时，则高、低位异步清零elsif(clk'event and clk='1')then否则 clk 为上升沿时if(counter<5)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;end if;carry_out1<='0'若高位 counter<5, 低位

11、 count=9 ，则低位清零，高位进 1，否则低位进 1，59 分时的进位信号 carry_out1 为 0 elseif(count=9)thencount<="0000"counter<="0000"carry_out1<='1'若高位counter 为 5 时，低位 count=9 ，则高、低位清零，59 分时的进位信号carry_out1进位为 1。elsecount<=count+1;carry_out1<='0'低位 count 加 1，59 分时的进位信号carry_out1为

12、 0。end if;end if;end if;end process;p2:process(reset,clk)beginif(clk'event and clk='0')then若 clk 为下降沿时if(counter=0)thenif(count=0)thencarry_out2<='0'若高位counter 为零，低位为零，则59 分时的进位信号carry_out2为 0end if;elsecarry_out2<='1' 否则进位为 1 end if;end if;end process;daout_ma(7 do

13、wnto 4)<=counter;高位赋予daout_madaout_mb(3 downto 0)<=count;低位赋予daout_mbenhour<=(carry_out1 and carry_out2)or sethour;程序两个59 分的进位信号或手动给enmin 进位end behav;3. 小时模块设计（ 24 小时制） library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity xiaoshi is port(reset,clk:in std_logic;d

14、aout_ha:out std_logic_vector(7 downto 4); 输出高位 daout_hadaout_hb:out std_logic_vector(3 downto 0); 输出地位 daout_hbend xiaoshi;architecture behav of xiaoshi issignal count:std_logic_vector(3 downto 0); signal counter:std_logic_vector(3 downto 0); beginp1:process(reset,clk) beginif reset='0'then

15、count<="0000"counter<="0000"若 reset 为 0 时，则高、低位异步清零if(counter<2)thenelsif(clk'event and clk='1')then否则 clk 上升沿来到时if(counter<2)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;若高位counter<2, 低位 count=9 ，则低位清零，高位进 1，

16、否则低位进1。end if;elseif(count=3)thencount<="0000"counter<="0000"elsecount<=count+1;若高位counter=2, 低位count=3 ，则高、低位清零，否则低位进一。end if;end if;end if;end process;daout_ha(7 downto 4)<=counter;高位赋予daout_hadaout_hb(3 downto 0)<=count;地位赋予daout_hbend behav;4. 动态扫描模块设计 library

17、ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seltime isport(ckdsp:in std_logic; reset:in std_logic;shijian_s:in std_logic_vector(7 downto 4);秒模块高位模块输入shijian_g:in std_logic_vector(3 downto 0);秒模块低位模块输入fen_s:in std_logic_vector(7 downto 4);fen_g:in std_logic_vector(3 down

18、to 0); xiaoshi_s:in std_logic_vector(7 downto 4); xiaoshi_g:in std_logic_vector(3 downto 0); daout:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0);end seltime;architecture behav of seltime issignal sec:std_logic_vector(2 downto 0);beginprocess(reset,ckdsp)beginif(reset='0&

19、#39;)thensec<="000"elsif(ckdsp'event and ckdsp='1')thenif(sec="101")thensec<="000"elsesec<=sec+1;end if;end if;end process;process(sec,shijian_g,shijian_s,fen_g,fen_s,xiaoshi_g,xiaoshi_s)begincase sec iswhen"000"=>daout<=shijian_g(3

20、downto 0); when"001"=>daout<=shijian_s(7 downto 4); when"010"=>daout<=fen_g(3 downto 0); when"011"=>daout<=fen_s(7 downto 4); when"100"=>daout<=xiaoshi_g(3 downto 0); when"101"=>daout<=xiaoshi_s(7 downto 4); when others=

21、>daout<="xxxx" end case;end process;sel<=sec;end behav;5. 整点报时模式 library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alert isport(clkspk:in std_logic;时钟信号shijian_s:in std_logic_vector(7 downto 4);shijian_g:in std_logic_vector(3 downto 0);fen_s:in std_

22、logic_vector(7 downto 4);fen_g:in std_logic_vector(3 downto 0);speak:out std_logic;输出 speaklamp:out std_logic_vector(8 downto 0);输出 lampend alert;architecture behav of alert issignal divclkspk2:std_logic;beginp1:process(clkspk)beginif(clkspk'event and clkspk='1')then当 clkspk为上升沿时divclksp

23、k2<=not divclkspk2; divclkspk2 的非赋予 divclkspk2 end if;end process;p2:process(shijian_s,shijian_g,fen_s,fen_g) beginif(fen_g="1001"andfen_s="0101"andshijian_s="0101")then若时间是59 分 50 秒时case shijian_g is隔一秒响一次when"0001"=>lamp<="000000001"speak&

24、lt;=divclkspk2;when"0010"=>lamp<="000000010"speak<='0'when"0011"=>lamp<="000000100"speak<=divclkspk2;when"0100"=>lamp<="000001000"speak<='0'when"0101"=>lamp<="000010000"sp

25、eak<=divclkspk2;when"0110"=>lamp<="000100000"speak<='0'when"0111"=>lamp<="001000000"speak<=divclkspk2;when"1000"=>lamp<="010000000"speak<='0'when"1001"=>lamp<="100000000&quo

26、t;speak<=clkspk;当 59 秒信号给 lamp，时钟信号给speak，准备整点报时when others=>lamp<="000000000"当秒为其他值时无效end case;end if;end process;end behav;6.7 段译码显示模块设计library ieee;use ieee.std_logic_1164.all;entity deled isport(s:in std_logic_vector(3 downto 0);a,b,c,d,e,f,g,h:out std_logic);end deled;archite

27、cture behav of deled issignal data:std_logic_vector(3 downto 0);signal dout:std_logic_vector(7 downto 0);begindata<=s; s 赋值给 dataprocess(data)begincase data iswhen"0000"=>dout<="00111111"当 data 是 0000时将 00111111赋给 doutwhen"0001"=>dout<="00000110"

28、;when"0010"=>dout<="01011011"when"0011"=>dout<="01001111"when"0100"=>dout<="01100110"when"0101"=>dout<="01101101"when"0110"=>dout<="01111101"when"0111"=>dout

29、<="00000111"when"1000"=>dout<="01111111"when"1001"=>dout<="01101111"when"1010"=>dout<="01110111"when"1011"=>dout<="01111100"when"1100"=>dout<="00111001"when"1101"=>dout<="01011110"when"1110"=>dout<="01111001"when"1111"=>dout<="01110001"when others=>dout<="00000000"当 data 为其他值时，将 00000000赋给