Aug_28_1. SHARC

1、The World Leader in High Performance Signal Processing SolutionsSHARC Update2008 Aug.SHARC UpdateFloating Point Processors for a Broad Range of ApplicationsAutomotiveConsumerElectronicsProfessional AudioMedical, Industrial andInstrumentationSHARC DSP product PortfolioSHARC architectureSHARC Processo

2、rsuIn this workshop we will cover the ADSP-21368/9, ADSP-21375uAll ADSP-2136x and 7x SHARC processors share a common core architecturelAll are code compatiblelThe main differences are:u Amounts of on-chip memory, RAM and/or ROMuPeripheral setsuExternal interfaceuProcessor speeduThere are Audio speci

3、fic SHARCs which have several of the standard audio algorithms in ROM. These SHARCs require licensing to purchase. We will not be covering these in the workshop. However because they are all code compatible, function and code development do applyuRefer to our web site for a complete list of all SHAR

4、Cs Our Strategy:Supply Effective Solutions for Real World Signal Processing ApplicationsSignal ConditioningDataConversionDigital SignalProcessingExternalSystemHostComputerWhat are the characteristics of a Good DSP?uFast, flexible arithmetic computation unitsuUnconstrained data flow to and from the c

5、omputation unitsuExtended precision and dynamic range in the computation unitsuDual address generatorsuEfficient program sequencinguEase of programminguEfficient I/O ProcessingADSP-2136x DSP Core FeaturesuFast arithmetic processing capabilitieslTwo processing elements, each containing: Register File

6、, ALU, Multiplier/MAC, ShifteruParallel operation of ALU and Multiplier within each processing elementuNo arithmetic Pipelining:l Register File -to- Arithmetic -to- Register File within instruction cyclelExtended dynamic rangeu32/40-bit IEEE floating point dynamic range is 10E-38 to 10E+38u32-bit fi

7、xed point MACs with 80-bit accumulationuSingle-cycle Multiple data transferslTwo independent Data Address Generators (DAGs) support multiple data accesses in a single cycleuCircular buffer addressing supported in hardwarelBoth DAGs support circular bufferinguZero overhead looping in hardware, 6 leve

8、ls deepADSP-2136x DSP Core Features Single-Instruction, Multiple-Data (SIMD)uSIMD is used to increase the arithmetic throughput of the DSPuIn SIMD mode, the same arithmetic operation is performed on two sets of data within the same instruction cycleuSIMD is supported by two similar Processing Elemen

9、ts PEx and PEylPEx is the primary processing element and processes all computational instructions whether in Single Instruction, Single-Data (SISD) or in SIMD modelPEy is the secondary processing element and processes each computational instruction in lock-step with PEx when SIMD is enableduThe DAGs

10、 can supply data for both processing elements at the instruction cycle rateDSP CoreCache64Data Memory Data (DMD)Program Memory Data (PMD)64Data Memory Address (DAG 1)32Program Memory Address (DAG 2)32InternalMemoryThe Modified Harvard ArchitectureThe Modified Harvard ArchitectureuInstructions are fe

11、tched every cycle over the Program Memory bus unless cacheduData Memory accesses have precedence over Program Memory data accesses uPM Bus conflicts occur when instruction fetch and PM data fetch are required inthe same cycle (cache miss) IO AddressIO DataIOProcessor3224Material available at websiteuHardware ReferenceuInstruction Set ReferenceuApplication NotesuData SheetsuVisualDSP+ Manual SetlAssem